The most recent version of this page is a draft.DiffThis version (14 Mar 2023 06:11) was approved by Joyce Velasco.The Previously approved version (09 Mar 2023 02:08) is available.Diff

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Schematic, PCB Layout, Bill of Materials

AD-FMCOMMS5-EBZ Design & Integration Files

I/O Voltage

The AD-FMCOMMS5-EBZ (AD9361) assumes a VDD_INTERFACE voltage between 1.71V and 2.625V (1.8 to 2.5 +/- 5%), so on your FPGA carrier board, you should ensure that VADJ is between these levels. Setting things to 3.3V will damage the part.

Phase Synchronization

Traces between baluns and SMAs are not phase-matched on REV-A and REV-B which can cause phase misalignment with the libad9361-iio ad9361_fmcomms5_phase_sync solution. This is corrected on REV-C. Therefore, phase alignment performance can vary over frequency. The RF switches on REV-A/B are also not designed to work above 900 MHz. Higher frequency switches are available on REV-C.

Below are some preliminary results using Release 2018-R1 with equal length but unmatched cables

Rev B

Rev C

/srv/ · Last modified: 14 Mar 2023 06:13 by Joyce Velasco