This version is outdated by a newer approved version.DiffThis version (25 Mar 2014 21:28) was approved by Robin Getz, Vinod Gopalakrishnan.

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I/O Voltage

The AD-FMComms4 (AD9364) assumes a VDD_INTERFACE voltage between 1.71V and 2.625V (1.8 to 2.5 +/- 5%), so on your FPGA carrier board, you should ensure that VADJ is between these levels. Setting things to 3.3V will damage the part.

resources/eval/user-guides/ad-fmcomms4-ebz/hardware.1395779319.txt.gz · Last modified: 25 Mar 2014 21:28 by Robin Getz