| Both sides previous revisionPrevious revision | |
| resources:eval:user-guides:ad-fmcomms3-ebz:hardware [28 Jan 2021 19:57] – update arrow links after their web site update Robin Getz | resources:eval:user-guides:ad-fmcomms3-ebz:hardware [09 Mar 2023 01:35] (current) – updated the design files download link Joyce Velasco |
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| ====== AD-FMCOMMS3-EBZ Hardware ====== | ====== AD-FMCOMMS3-EBZ Hardware ====== |
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| ===== Downloads ===== | ===== Schematic, PCB Layout, Bill of Materials ===== |
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| <WRAP round download 65%> | <WRAP round download 65%> |
| <WRAP info>This is the latest, greatest and production worthy Rev "A" of this board (Although it indicates "A", this is not the first version, and there is no Rev B planned). Note that the RF transformers used as baluns on the Rev A board are Mini Circuits [[http://www.minicircuits.com/pdfs/TCM1-63AX+.pdf|TCM1-63AX+]]. They are rated for a operating frequency between 10 MHz and 6 GHz. | <WRAP info>This is the latest, greatest and production worthy Rev "A" of this board (Although it indicates "A", this is not the first version, and there is no Rev B planned). |
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| | Note that the RF transformers used as baluns on the Rev A board are Mini Circuits [[http://www.minicircuits.com/pdfs/TCM1-63AX+.pdf|TCM1-63AX+]]. They are rated for an operating frequency between 10 MHz and 6 GHz. |
| </WRAP> | </WRAP> |
| | [[adi>media/en/reference-design-documentation/design-integration-files/ad-fmcomms3-ebz-designsupport.zip|AD-FMCOMMS3-EBZ Design & Integration Files]] |
| * {{:resources:eval:user-guides:ad-fmcomms3-ebz:ad-fmcomms3_reva.pdf|Rev A Schematics}} | * Schematic |
| * {{:resources:eval:user-guides:ad-fmcomms3-ebz:ad-fmcomms3_reva.zip|Rev A Gerbers}} | * PCB Layout |
| * {{:resources:eval:user-guides:ad-fmcomms3-ebz:ad-fmcomms3_reva.xls|Rev A Bill of materials}} | * Bill of Materials |
| * {{:resources:eval:user-guides:ad-fmcomms3-ebz:ad-fmcomms3_reva.brd.7z|Rev A Allegro Board File}} (This file is [[http://www.7-zip.org/7z.html|compressed]]). Get the [[https://www.cadence.com/en_US/home/tools/pcb-design-and-analysis/allegro-downloads-start.html|Allegro FREE Physical Viewer]] (You need 16.5 or higher). | * Allegro Project (get the [[https://www.cadence.com/en_US/home/tools/pcb-design-and-analysis/allegro-downloads-start.html|Allegro FREE Physical Viewer]]; you need 16.5 or higher) |
| </WRAP> | </WRAP> |
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| ===== I/O Voltage ===== | ===== I/O Voltage ===== |
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| The AD-FMComms3 (AD9361) assumes a VDD_INTERFACE voltage between 1.71V and 2.625V (1.8 to 2.5 +/- 5%), so on your FPGA carrier board, you should ensure that V<sub>ADJ</sub> is between these levels. Setting things to 3.3V will damage the part. | The [[ADI>AD-FMCOMMS3-EBZ]] (AD9361) assumes a VDD_INTERFACE voltage between 1.71V and 2.625V (1.8 to 2.5 +/- 5%), so on your FPGA carrier board, you should ensure that V<sub>ADJ</sub> is between these levels. Setting things to 3.3V will damage the part. |
| ===== Picture and Main components ===== | ===== Picture and Main components ===== |
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