| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| resources:eval:user-guides:ad-fmcomms2-ebz:software:baremetal [19 Jan 2015 22:36] – library path incorrect on ad9361 command.c file for ad9361_api.h .. should change git repo... Allen Roth | resources:eval:user-guides:ad-fmcomms2-ebz:software:baremetal [18 Sep 2023 09:26] (current) – update build instructions Darius B |
|---|
| ====== AD9361 No-OS Software ====== | ====== AD9361 No-OS Software ====== |
| | |
| | The AD9361 is a high performance, highly integrated RF Agile Transceiver™. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. |
| | |
| | ===== Supported Devices ===== |
| | |
| | * [[adi>AD9361]] |
| | * [[adi>AD9363]] |
| | * [[adi>AD9364]] |
| |
| ===== Introduction ===== | ===== Introduction ===== |
| (struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)</code>|Gets current RF bandwidth. Receives as parameters a structure that contains the AD9361 current state and a variable to store the bandwidth value in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)</code>|Gets current RF bandwidth. Receives as parameters a structure that contains the AD9361 current state and a variable to store the bandwidth value in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_rx_sampling_freq | |<code c>int32_t ad9361_set_rx_sampling_freq |
| (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)</code>|Sets the sampling frequency. Receives as parameters a structure that contains the AD9361 current state and the desired frequency in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)</code>|Sets the sampling frequency. Receives as parameters a structure that contains the AD9361 current state and the desired sampling frequency in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_get_rx_sampling_freq | |<code c>int32_t ad9361_get_rx_sampling_freq |
| (struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz)</code>|Gets current sampling frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz)</code>|Gets current sampling frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the sampling frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_rx_lo_freq | |<code c>int32_t ad9361_set_rx_lo_freq |
| (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)</code>|Sets the LO frequency. Receives as parameters a structure that contains the AD9361 current state and the desired frequency in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)</code>|Sets the LO frequency. Receives as parameters a structure that contains the AD9361 current state and the desired LO frequency in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_get_rx_lo_freq | |<code c>int32_t ad9361_get_rx_lo_freq |
| (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz)</code>|Gets current LO frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz)</code>|Gets current LO frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the LO frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext)</code>|Switches between internal and external LO. Receives as parameters a structure that contains the AD9361 current state and the desired option (INT_LO, EXT_LO). Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_get_rx_rssi | |<code c>int32_t ad9361_get_rx_rssi |
| (struct ad9361_rf_phy *phy, uint8_t ch, struct rf_rssi *rssi)</code>|Gets the RSSI for the selected channel. Receives as parameters a structure that contains the AD9361 current state, the desired channel (0, 1) and a variable to store the RSSI. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint8_t ch, struct rf_rssi *rssi)</code>|Gets the RSSI for the selected channel. Receives as parameters a structure that contains the AD9361 current state, the desired channel (0, 1) and a variable to store the RSSI. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_rx_fir_config | |<code c>int32_t ad9361_set_rx_fir_config |
| (struct ad9361_rf_phy *phy, AD9361_RXFIRConfig fir_cfg)</code>|Sets the FIR filter configuration. Receives as parameters a structure that contains the AD9361 current state and the FIR filter configuration. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, AD9361_RXFIRConfig fir_cfg)</code>|Sets the FIR filter configuration. Receives as parameters a structure that contains the AD9361 current state and the FIR filter configuration. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch, AD9361_RXFIRConfig *fir_cfg)</code>|Gets the RX FIR filter configuration. Receives as parameters a structure that contains the AD9361 current state, the desired channel (RX1, RX2) and the location for storing the FIR filter configuration. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_rx_fir_en_dis | |<code c>int32_t ad9361_set_rx_fir_en_dis |
| (struct ad9361_rf_phy *phy, uint8_t en_dis)</code>|Enables/disables the FIR filter. Receives as parameters a structure that contains the AD9361 current state and the option (ENABLE, DISABLE). Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint8_t en_dis)</code>|Enables/disables the FIR filter. Receives as parameters a structure that contains the AD9361 current state and the option (ENABLE, DISABLE). Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_get_rx_quad_track_en_dis | |<code c>int32_t ad9361_get_rx_quad_track_en_dis |
| (struct ad9361_rf_phy *phy, uint8_t *en_dis)</code>|Gets the status of the RX Quadrature Tracking. Receives as parameters a structure that contains the AD9361 current state and the enable/disable status buffer.Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint8_t *en_dis)</code>|Gets the status of the RX Quadrature Tracking. Receives as parameters a structure that contains the AD9361 current state and the enable/disable status buffer.Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_set_rx_rf_port_input (struct ad9361_rf_phy *phy,uint32_t mode)</code>|Sets the RX RF input port. Receives as parameters a structure that contains the AD9361 current state and the desired port (A_BALANCED, B_BALANCED, C_BALANCED, A_N, A_P, B_N, B_P, C_N, C_P, TX_MON1, TX_MON2, TX_MON1_2). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_rx_rf_port_input (struct ad9361_rf_phy *phy,uint32_t *mode)</code>|Gets the selected RX RF input port. Receives as parameters a structure that contains the AD9361 current state and the location to store the selected port value. Returns 0 in case of success, negative error code otherwise. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile)</code>|Stores RX fastlock profile. To create a profile tune the synthesizer (ad9361_set_rx_lo_freq()) and then call this function specifying the target profile number. Receives as parameters a structure that contains the AD9361 current state and the profile number (0 - 7). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile)</code>|Recalls specified RX fastlock profile. When in fastlock pin select mode (init_param->rx_fastlock_pincontrol_enable), the function needs to be called before then the pin-control can be used. Receives as parameters a structure that contains the AD9361 current state and the profile number (0 - 7). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)</code>|Recalls specified RX fastlock profile. When in fastlock pin select mode (init_param->rx_fastlock_pincontrol_enable), the function needs to be called before then the pin-control can be used. Receives as parameters a structure that contains the AD9361 current state, the profile number (0 - 7) and the Fastlock profile program data (val0,val1,val2,...,val15). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)</code>|Saves RX fastlock profile. In order to use more than 8 Profiles, an existing profile can be read back and stored by the user application. Receives as parameters a structure that contains the AD9361 current state, the profile number (0 - 7) and the location for storing the profile data. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option)</code>|Powers down the RX Local Oscillator. Receives as parameters a structure that contains the AD9361 current state and the option (ON, OFF). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option)</code>|Gets the RX Local Oscillator power status. Receives as parameters a structure that contains the AD9361 current state and the location to store the selected option. Returns 0 in case of success, negative error code otherwise.| |
| ^ Transmit Chain Settings ^^ | ^ Transmit Chain Settings ^^ |
| |<code c>int32_t ad9361_set_tx_attenuation | |<code c>int32_t ad9361_set_tx_attenuation |
| (struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)</code>|Gets current RF bandwidth. Receives as parameters a structure that contains the AD9361 current state and a variable to store the bandwidth value in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint32_t *bandwidth_hz)</code>|Gets current RF bandwidth. Receives as parameters a structure that contains the AD9361 current state and a variable to store the bandwidth value in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_tx_sampling_freq | |<code c>int32_t ad9361_set_tx_sampling_freq |
| (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)</code>|Sets the sampling frequency. Receives as parameters a structure that contains the AD9361 current state and the desired frequency in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz)</code>|Sets the sampling frequency. Receives as parameters a structure that contains the AD9361 current state and the desired sampling frequency in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_get_tx_sampling_freq | |<code c>int32_t ad9361_get_tx_sampling_freq |
| (struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz)</code>|Gets current sampling frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint32_t *sampling_freq_hz)</code>|Gets current sampling frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the sampling frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_tx_lo_freq | |<code c>int32_t ad9361_set_tx_lo_freq |
| (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)</code>|Sets the LO frequency. Receives as parameters a structure that contains the AD9361 current state and the desired frequency in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz)</code>|Sets the LO frequency. Receives as parameters a structure that contains the AD9361 current state and the desired LO frequency in Hz. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_get_tx_lo_freq | |<code c>int32_t ad9361_get_tx_lo_freq |
| (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz)</code>|Gets current LO frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz)</code>|Gets current LO frequency. Receives as parameters a structure that contains the AD9361 current state and a variable to store the LO frequency value in Hz. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext)</code>|Switches between internal and external LO. Receives as parameters a structure that contains the AD9361 current state and the desired option (INT_LO, EXT_LO). Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_tx_fir_config | |<code c>int32_t ad9361_set_tx_fir_config |
| (struct ad9361_rf_phy *phy, AD9361_TXFIRConfig fir_cfg)</code>|Sets the FIR filter configuration. Receives as parameters a structure that contains the AD9361 current state and the FIR filter configuration. Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, AD9361_TXFIRConfig fir_cfg)</code>|Sets the FIR filter configuration. Receives as parameters a structure that contains the AD9361 current state and the FIR filter configuration. Returns 0 in case of success, negative error code otherwise.| |
| | |
| | |<code c>int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch, AD9361_TXFIRConfig *fir_cfg)</code>|Gets the TX FIR filter configuration. Receives as parameters a structure that contains the AD9361 current state and the location to store the FIR filter configuration. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_tx_fir_en_dis | |<code c>int32_t ad9361_set_tx_fir_en_dis |
| (struct ad9361_rf_phy *phy, uint8_t en_dis)</code>|Enables/disables the FIR filter. Receives as parameters a structure that contains the AD9361 current state and the option (ENABLE, DISABLE). Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint8_t en_dis)</code>|Enables/disables the FIR filter. Receives as parameters a structure that contains the AD9361 current state and the option (ENABLE, DISABLE). Returns 0 in case of success, negative error code otherwise.| |
| uint8_t ch, | uint8_t ch, |
| uint32_t *rssi_db_x_1000)</code>|Gets the TX RSSI for the selected channel. Receives as parameters a structure that contains the AD9361 current state, the desired channel (0, 1) and a variable to store the RSSI. Returns 0 in case of success, negative error code otherwise.| | uint32_t *rssi_db_x_1000)</code>|Gets the TX RSSI for the selected channel. Receives as parameters a structure that contains the AD9361 current state, the desired channel (0, 1) and a variable to store the RSSI. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_set_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t mode)</code>|Sets the TX RF output port. Receives as parameters a structure that contains the AD9361 current state and the desired port (TXA, TXB). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t *mode)</code>|Gets the selected TX RF output port. Receives as parameters a structure that contains the AD9361 current state and the location for storing the selected port. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_set_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis)</code>|Enables/disables the auto calibration. Receives as parameters a structure that contains the AD9361 current state and the desired mode (ENABLE, DISABLE). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis)</code>|Gets the status of the auto calibration flag. Receives as parameters a structure that contains the AD9361 current state and the location for storing the selected mode. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile)</code>|Stores TX fastlock profile. Receives as parameters a structure that contains the AD9361 current state and the profile number (0 - 7). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile)</code>|Recalls specified TX fastlock profile. Receives as parameters a structure that contains the AD9361 current state and the profile number (0 - 7). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)</code>|Loads TX fastlock profile. A previously saved profile can be loaded in any of the 8 available slots. Receives as parameters a structure that contains the AD9361 current state, the profile number (0 - 7) and the Fastlock profile program data (val0,val1,val2,...,val15). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile, uint8_t *values)</code>|Saves TX fastlock profile. In order to use more than 8 Profiles, an existing profile can be read back and stored by the user application. Receives as parameters a structure that contains the AD9361 current state, the profile number (0 - 7) and the location for storing the profile data. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option)</code>|Powers down the TX Local Oscillator. Receives as parameters a structure that contains the AD9361 current state and the desired option (ON, OFF). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option)</code>|Gets the TX Local Oscillator power status. Receives as parameters a structure that contains the AD9361 current state and the location to store the selected option. Returns 0 in case of success, negative error code otherwise.| |
| |<code c>int32_t ad9361_set_trx_path_clks | |<code c>int32_t ad9361_set_trx_path_clks |
| (struct ad9361_rf_phy *phy, | (struct ad9361_rf_phy *phy, |
| |<code c>int32_t ad9361_set_no_ch_mode | |<code c>int32_t ad9361_set_no_ch_mode |
| (struct ad9361_rf_phy *phy, uint8_t no_ch_mode)</code>|Set the number of channels mode. Receives as parameters a structure that contains the AD9361 current state and the number of channels mode (1 - 1x1; 2 - 2x2). Returns 0 in case of success, negative error code otherwise.| | (struct ad9361_rf_phy *phy, uint8_t no_ch_mode)</code>|Set the number of channels mode. Receives as parameters a structure that contains the AD9361 current state and the number of channels mode (1 - 1x1; 2 - 2x2). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master, struct ad9361_rf_phy *phy_slave)</code>|Do multi chip synchronization. Receives as parameters a structure that contains the AD9361 master current state and a structure that contains the AD9361 slave current state. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_set_trx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis)</code>|Enables/disables the TRX FIR filters. Receives as parameters a structure that contains the AD9361 current state and the desired option (ENABLE, DISABLE). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_set_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t rate_gov)</code>|Set the OSR rate governor. Receives as parameters a structure that contains the AD9361 current state and the desired OSR rate governor (HIGHEST_OSR, NOMINAL_OSR). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t *rate_gov)</code>|Gets the OSR rate governor. Receives as parameters a structure that contains the AD9361 master current state and the location for storing the OSR rate governor. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)</code>|Performs the selected calibration. Receives as parameters a structure that contains the AD9361 current state, the desired calibration (TX_QUAD_CAL, RFDC_CAL) and for TX_QUAD_CAL, the optional RX phase value overwrite (set to zero). Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy, AD9361_RXFIRConfig rx_fir_cfg, AD9361_TXFIRConfig tx_fir_cfg)</code>|Loads and enables TRX FIR filters configurations. Receives as parameters a structure that contains the AD9361 current state, the RX FIR filter configuration and the TX FIR filter configuration. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy, uint32_t coarse)</code>|Does DCXO coarse tuning. Receives as parameters a structure that contains the AD9361 current state and the DCXO coarse tuning value. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy, uint32_t fine)</code>|Does DCXO fine tuning. Receives as parameters a structure that contains the AD9361 current state and the DCXO fine tuning value. Returns 0 in case of success, negative error code otherwise.| |
| | |<code c>int32_t ad9361_get_temperature(struct ad9361_rf_phy *phy, int32_t *temp)</code>|Gets the temperature. Receives as parameters a structure that contains the AD9361 current state and the location for storing the current temperature (degrees C * 1000). Returns 0 in case of success, negative error code otherwise.| |
| |
| **Notes:** | **Notes:** |
| |
| <code C> | <code C> |
| typedef struct | typedef struct |
| { | { |
| /* Identification number */ | /* Device selection */ |
| uint8_t id_no; | enum dev_id dev_sel; |
| /* Reference Clock */ | /* Identification number */ |
| uint32_t reference_clk_rate; | uint8_t id_no; |
| /* Base Configuration */ | /* Reference Clock */ |
| uint8_t two_rx_two_tx_mode_enable; /* adi,2rx-2tx-mode-enable */ | uint32_t reference_clk_rate; |
| uint8_t frequency_division_duplex_mode_enable; /* adi,frequency-division-duplex-mode-enable */ | /* Base Configuration */ |
| uint8_t tdd_use_dual_synth_mode_enable; /* adi,tdd-use-dual-synth-mode-enable */ | uint8_t two_rx_two_tx_mode_enable; /* adi,2rx-2tx-mode-enable */ |
| uint8_t tdd_skip_vco_cal_enable; /* adi,tdd-skip-vco-cal-enable */ | uint8_t one_rx_one_tx_mode_use_rx_num; /* adi,1rx-1tx-mode-use-rx-num */ |
| uint32_t tx_fastlock_delay_ns; /* adi,tx-fastlock-delay-ns */ | uint8_t one_rx_one_tx_mode_use_tx_num; /* adi,1rx-1tx-mode-use-tx-num */ |
| uint32_t rx_fastlock_delay_ns; /* adi,rx-fastlock-delay-ns */ | uint8_t frequency_division_duplex_mode_enable; /* adi,frequency-division-duplex-mode-enable */ |
| uint8_t rx_fastlock_pincontrol_enable; /* adi,rx-fastlock-pincontrol-enable */ | uint8_t frequency_division_duplex_independent_mode_enable; /* adi,frequency-division-duplex-independent-mode-enable */ |
| uint8_t tx_fastlock_pincontrol_enable; /* adi,tx-fastlock-pincontrol-enable */ | uint8_t tdd_use_dual_synth_mode_enable; /* adi,tdd-use-dual-synth-mode-enable */ |
| uint8_t external_rx_lo_enable; /* adi,external-rx-lo-enable */ | uint8_t tdd_skip_vco_cal_enable; /* adi,tdd-skip-vco-cal-enable */ |
| uint8_t external_tx_lo_enable; /* adi,external-tx-lo-enable */ | uint32_t tx_fastlock_delay_ns; /* adi,tx-fastlock-delay-ns */ |
| uint8_t dc_offset_tracking_update_event_mask; /* adi,dc-offset-tracking-update-event-mask */ | uint32_t rx_fastlock_delay_ns; /* adi,rx-fastlock-delay-ns */ |
| uint8_t dc_offset_attenuation_high_range; /* adi,dc-offset-attenuation-high-range */ | uint8_t rx_fastlock_pincontrol_enable; /* adi,rx-fastlock-pincontrol-enable */ |
| uint8_t dc_offset_attenuation_low_range; /* adi,dc-offset-attenuation-low-range */ | uint8_t tx_fastlock_pincontrol_enable; /* adi,tx-fastlock-pincontrol-enable */ |
| uint8_t dc_offset_count_high_range; /* adi,dc-offset-count-high-range */ | uint8_t external_rx_lo_enable; /* adi,external-rx-lo-enable */ |
| uint8_t dc_offset_count_low_range; /* adi,dc-offset-count-low-range */ | uint8_t external_tx_lo_enable; /* adi,external-tx-lo-enable */ |
| uint8_t tdd_use_fdd_vco_tables_enable; /* adi,tdd-use-fdd-vco-tables-enable */ | uint8_t dc_offset_tracking_update_event_mask; /* adi,dc-offset-tracking-update-event-mask */ |
| uint8_t split_gain_table_mode_enable; /* adi,split-gain-table-mode-enable */ | uint8_t dc_offset_attenuation_high_range; /* adi,dc-offset-attenuation-high-range */ |
| uint32_t trx_synthesizer_target_fref_overwrite_hz; /* adi,trx-synthesizer-target-fref-overwrite-hz */ | uint8_t dc_offset_attenuation_low_range; /* adi,dc-offset-attenuation-low-range */ |
| uint8_t qec_tracking_slow_mode_enable; /* adi,qec-tracking-slow-mode-enable */ | uint8_t dc_offset_count_high_range; /* adi,dc-offset-count-high-range */ |
| /* ENSM Control */ | uint8_t dc_offset_count_low_range; /* adi,dc-offset-count-low-range */ |
| uint8_t ensm_enable_pin_pulse_mode_enable; /* adi,ensm-enable-pin-pulse-mode-enable */ | uint8_t split_gain_table_mode_enable; /* adi,split-gain-table-mode-enable */ |
| uint8_t ensm_enable_txnrx_control_enable; /* adi,ensm-enable-txnrx-control-enable */ | uint32_t trx_synthesizer_target_fref_overwrite_hz; /* adi,trx-synthesizer-target-fref-overwrite-hz */ |
| /* LO Control */ | uint8_t qec_tracking_slow_mode_enable; /* adi,qec-tracking-slow-mode-enable */ |
| uint64_t rx_synthesizer_frequency_hz; /* adi,rx-synthesizer-frequency-hz */ | /* ENSM Control */ |
| uint64_t tx_synthesizer_frequency_hz; /* adi,tx-synthesizer-frequency-hz */ | uint8_t ensm_enable_pin_pulse_mode_enable; /* adi,ensm-enable-pin-pulse-mode-enable */ |
| /* Rate & BW Control */ | uint8_t ensm_enable_txnrx_control_enable; /* adi,ensm-enable-txnrx-control-enable */ |
| uint32_t rx_path_clock_frequencies[6]; /* adi,rx-path-clock-frequencies */ | /* LO Control */ |
| uint32_t tx_path_clock_frequencies[6]; /* adi,tx-path-clock-frequencies */ | uint64_t rx_synthesizer_frequency_hz; /* adi,rx-synthesizer-frequency-hz */ |
| uint32_t rf_rx_bandwidth_hz; /* adi,rf-rx-bandwidth-hz */ | uint64_t tx_synthesizer_frequency_hz; /* adi,tx-synthesizer-frequency-hz */ |
| uint32_t rf_tx_bandwidth_hz; /* adi,rf-tx-bandwidth-hz */ | uint8_t tx_lo_powerdown_managed_enable; /* adi,tx-lo-powerdown-managed-enable */ |
| /* RF Port Control */ | /* Rate & BW Control */ |
| uint32_t rx_rf_port_input_select; /* adi,rx-rf-port-input-select */ | uint32_t rx_path_clock_frequencies[6]; /* adi,rx-path-clock-frequencies */ |
| uint32_t tx_rf_port_input_select; /* adi,tx-rf-port-input-select */ | uint32_t tx_path_clock_frequencies[6]; /* adi,tx-path-clock-frequencies */ |
| /* TX Attenuation Control */ | uint32_t rf_rx_bandwidth_hz; /* adi,rf-rx-bandwidth-hz */ |
| int32_t tx_attenuation_mdB; /* adi,tx-attenuation-mdB */ | uint32_t rf_tx_bandwidth_hz; /* adi,rf-tx-bandwidth-hz */ |
| uint8_t update_tx_gain_in_alert_enable; /* adi,update-tx-gain-in-alert-enable */ | /* RF Port Control */ |
| /* Reference Clock Control */ | uint32_t rx_rf_port_input_select; /* adi,rx-rf-port-input-select */ |
| uint8_t xo_disable_use_ext_refclk_enable; /* adi,xo-disable-use-ext-refclk-enable */ | uint32_t tx_rf_port_input_select; /* adi,tx-rf-port-input-select */ |
| uint32_t dcxo_coarse_and_fine_tune[2]; /* adi,dcxo-coarse-and-fine-tune */ | /* TX Attenuation Control */ |
| uint32_t clk_output_mode_select; /* adi,clk-output-mode-select */ | int32_t tx_attenuation_mdB; /* adi,tx-attenuation-mdB */ |
| /* Gain Control */ | uint8_t update_tx_gain_in_alert_enable; /* adi,update-tx-gain-in-alert-enable */ |
| uint8_t gc_rx1_mode; /* adi,gc-rx1-mode */ | /* Reference Clock Control */ |
| uint8_t gc_rx2_mode; /* adi,gc-rx2-mode */ | uint8_t xo_disable_use_ext_refclk_enable; /* adi,xo-disable-use-ext-refclk-enable */ |
| uint8_t gc_adc_large_overload_thresh; /* adi,gc-adc-large-overload-thresh */ | uint32_t dcxo_coarse_and_fine_tune[2]; /* adi,dcxo-coarse-and-fine-tune */ |
| uint8_t gc_adc_ovr_sample_size; /* adi,gc-adc-ovr-sample-size */ | uint32_t clk_output_mode_select; /* adi,clk-output-mode-select */ |
| uint8_t gc_adc_small_overload_thresh; /* adi,gc-adc-small-overload-thresh */ | /* Gain Control */ |
| uint16_t gc_dec_pow_measurement_duration; /* adi,gc-dec-pow-measurement-duration */ | uint8_t gc_rx1_mode; /* adi,gc-rx1-mode */ |
| uint8_t gc_dig_gain_enable; /* adi,gc-dig-gain-enable */ | uint8_t gc_rx2_mode; /* adi,gc-rx2-mode */ |
| uint16_t gc_lmt_overload_high_thresh; /* adi,gc-lmt-overload-high-thresh */ | uint8_t gc_adc_large_overload_thresh; /* adi,gc-adc-large-overload-thresh */ |
| uint16_t gc_lmt_overload_low_thresh; /* adi,gc-lmt-overload-low-thresh */ | uint8_t gc_adc_ovr_sample_size; /* adi,gc-adc-ovr-sample-size */ |
| uint8_t gc_low_power_thresh; /* adi,gc-low-power-thresh */ | uint8_t gc_adc_small_overload_thresh; /* adi,gc-adc-small-overload-thresh */ |
| uint8_t gc_max_dig_gain; /* adi,gc-max-dig-gain */ | uint16_t gc_dec_pow_measurement_duration; /* adi,gc-dec-pow-measurement-duration */ |
| /* Gain MGC Control */ | uint8_t gc_dig_gain_enable; /* adi,gc-dig-gain-enable */ |
| uint8_t mgc_dec_gain_step; /* adi,mgc-dec-gain-step */ | uint16_t gc_lmt_overload_high_thresh; /* adi,gc-lmt-overload-high-thresh */ |
| uint8_t mgc_inc_gain_step; /* adi,mgc-inc-gain-step */ | uint16_t gc_lmt_overload_low_thresh; /* adi,gc-lmt-overload-low-thresh */ |
| uint8_t mgc_rx1_ctrl_inp_enable; /* adi,mgc-rx1-ctrl-inp-enable */ | uint8_t gc_low_power_thresh; /* adi,gc-low-power-thresh */ |
| uint8_t mgc_rx2_ctrl_inp_enable; /* adi,mgc-rx2-ctrl-inp-enable */ | uint8_t gc_max_dig_gain; /* adi,gc-max-dig-gain */ |
| uint8_t mgc_split_table_ctrl_inp_gain_mode; /* adi,mgc-split-table-ctrl-inp-gain-mode */ | /* Gain MGC Control */ |
| /* Gain AGC Control */ | uint8_t mgc_dec_gain_step; /* adi,mgc-dec-gain-step */ |
| uint8_t agc_adc_large_overload_exceed_counter; /* adi,agc-adc-large-overload-exceed-counter */ | uint8_t mgc_inc_gain_step; /* adi,mgc-inc-gain-step */ |
| uint8_t agc_adc_large_overload_inc_steps; /* adi,agc-adc-large-overload-inc-steps */ | uint8_t mgc_rx1_ctrl_inp_enable; /* adi,mgc-rx1-ctrl-inp-enable */ |
| uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable; /* adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable */ | uint8_t mgc_rx2_ctrl_inp_enable; /* adi,mgc-rx2-ctrl-inp-enable */ |
| uint8_t agc_adc_small_overload_exceed_counter; /* adi,agc-adc-small-overload-exceed-counter */ | uint8_t mgc_split_table_ctrl_inp_gain_mode; /* adi,mgc-split-table-ctrl-inp-gain-mode */ |
| uint8_t agc_dig_gain_step_size; /* adi,agc-dig-gain-step-size */ | /* Gain AGC Control */ |
| uint8_t agc_dig_saturation_exceed_counter; /* adi,agc-dig-saturation-exceed-counter */ | uint8_t agc_adc_large_overload_exceed_counter; /* adi,agc-adc-large-overload-exceed-counter */ |
| uint32_t agc_gain_update_interval_us; /* adi,agc-gain-update-interval-us */ | uint8_t agc_adc_large_overload_inc_steps; /* adi,agc-adc-large-overload-inc-steps */ |
| uint8_t agc_immed_gain_change_if_large_adc_overload_enable; /* adi,agc-immed-gain-change-if-large-adc-overload-enable */ | uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable; /* adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable */ |
| uint8_t agc_immed_gain_change_if_large_lmt_overload_enable; /* adi,agc-immed-gain-change-if-large-lmt-overload-enable */ | uint8_t agc_adc_small_overload_exceed_counter; /* adi,agc-adc-small-overload-exceed-counter */ |
| uint8_t agc_inner_thresh_high; /* adi,agc-inner-thresh-high */ | uint8_t agc_dig_gain_step_size; /* adi,agc-dig-gain-step-size */ |
| uint8_t agc_inner_thresh_high_dec_steps; /* adi,agc-inner-thresh-high-dec-steps */ | uint8_t agc_dig_saturation_exceed_counter; /* adi,agc-dig-saturation-exceed-counter */ |
| uint8_t agc_inner_thresh_low; /* adi,agc-inner-thresh-low */ | uint32_t agc_gain_update_interval_us; /* adi,agc-gain-update-interval-us */ |
| uint8_t agc_inner_thresh_low_inc_steps; /* adi,agc-inner-thresh-low-inc-steps */ | uint8_t agc_immed_gain_change_if_large_adc_overload_enable; /* adi,agc-immed-gain-change-if-large-adc-overload-enable */ |
| uint8_t agc_lmt_overload_large_exceed_counter; /* adi,agc-lmt-overload-large-exceed-counter */ | uint8_t agc_immed_gain_change_if_large_lmt_overload_enable; /* adi,agc-immed-gain-change-if-large-lmt-overload-enable */ |
| uint8_t agc_lmt_overload_large_inc_steps; /* adi,agc-lmt-overload-large-inc-steps */ | uint8_t agc_inner_thresh_high; /* adi,agc-inner-thresh-high */ |
| uint8_t agc_lmt_overload_small_exceed_counter; /* adi,agc-lmt-overload-small-exceed-counter */ | uint8_t agc_inner_thresh_high_dec_steps; /* adi,agc-inner-thresh-high-dec-steps */ |
| uint8_t agc_outer_thresh_high; /* adi,agc-outer-thresh-high */ | uint8_t agc_inner_thresh_low; /* adi,agc-inner-thresh-low */ |
| uint8_t agc_outer_thresh_high_dec_steps; /* adi,agc-outer-thresh-high-dec-steps */ | uint8_t agc_inner_thresh_low_inc_steps; /* adi,agc-inner-thresh-low-inc-steps */ |
| uint8_t agc_outer_thresh_low; /* adi,agc-outer-thresh-low */ | uint8_t agc_lmt_overload_large_exceed_counter; /* adi,agc-lmt-overload-large-exceed-counter */ |
| uint8_t agc_outer_thresh_low_inc_steps; /* adi,agc-outer-thresh-low-inc-steps */ | uint8_t agc_lmt_overload_large_inc_steps; /* adi,agc-lmt-overload-large-inc-steps */ |
| uint32_t agc_attack_delay_extra_margin_us; /* adi,agc-attack-delay-extra-margin-us */ | uint8_t agc_lmt_overload_small_exceed_counter; /* adi,agc-lmt-overload-small-exceed-counter */ |
| uint8_t agc_sync_for_gain_counter_enable; /* adi,agc-sync-for-gain-counter-enable */ | uint8_t agc_outer_thresh_high; /* adi,agc-outer-thresh-high */ |
| /* Fast AGC */ | uint8_t agc_outer_thresh_high_dec_steps; /* adi,agc-outer-thresh-high-dec-steps */ |
| uint32_t fagc_dec_pow_measuremnt_duration; /* adi,fagc-dec-pow-measurement-duration */ | uint8_t agc_outer_thresh_low; /* adi,agc-outer-thresh-low */ |
| uint32_t fagc_state_wait_time_ns; /* adi,fagc-state-wait-time-ns */ | uint8_t agc_outer_thresh_low_inc_steps; /* adi,agc-outer-thresh-low-inc-steps */ |
| /* Fast AGC - Low Power */ | uint32_t agc_attack_delay_extra_margin_us; /* adi,agc-attack-delay-extra-margin-us */ |
| uint8_t fagc_allow_agc_gain_increase; /* adi,fagc-allow-agc-gain-increase-enable */ | uint8_t agc_sync_for_gain_counter_enable; /* adi,agc-sync-for-gain-counter-enable */ |
| uint32_t fagc_lp_thresh_increment_time; /* adi,fagc-lp-thresh-increment-time */ | /* Fast AGC */ |
| uint32_t fagc_lp_thresh_increment_steps; /* adi,fagc-lp-thresh-increment-steps */ | uint32_t fagc_dec_pow_measuremnt_duration; /* adi,fagc-dec-pow-measurement-duration */ |
| /* Fast AGC - Lock Level */ | uint32_t fagc_state_wait_time_ns; /* adi,fagc-state-wait-time-ns */ |
| uint32_t fagc_lock_level; /* adi,fagc-lock-level */ | /* Fast AGC - Low Power */ |
| uint8_t fagc_lock_level_lmt_gain_increase_en; /* adi,fagc-lock-level-lmt-gain-increase-enable */ | uint8_t fagc_allow_agc_gain_increase; /* adi,fagc-allow-agc-gain-increase-enable */ |
| uint32_t fagc_lock_level_gain_increase_upper_limit; /* adi,fagc-lock-level-gain-increase-upper-limit */ | uint32_t fagc_lp_thresh_increment_time; /* adi,fagc-lp-thresh-increment-time */ |
| /* Fast AGC - Peak Detectors and Final Settling */ | uint32_t fagc_lp_thresh_increment_steps; /* adi,fagc-lp-thresh-increment-steps */ |
| uint32_t fagc_lpf_final_settling_steps; /* adi,fagc-lpf-final-settling-steps */ | /* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */ |
| uint32_t fagc_lmt_final_settling_steps; /* adi,fagc-lmt-final-settling-steps */ | uint8_t fagc_lock_level_lmt_gain_increase_en; /* adi,fagc-lock-level-lmt-gain-increase-enable */ |
| uint32_t fagc_final_overrange_count; /* adi,fagc-final-overrange-count */ | uint32_t fagc_lock_level_gain_increase_upper_limit; /* adi,fagc-lock-level-gain-increase-upper-limit */ |
| /* Fast AGC - Final Power Test */ | /* Fast AGC - Peak Detectors and Final Settling */ |
| uint8_t fagc_gain_increase_after_gain_lock_en; /* adi,fagc-gain-increase-after-gain-lock-enable */ | uint32_t fagc_lpf_final_settling_steps; /* adi,fagc-lpf-final-settling-steps */ |
| /* Fast AGC - Unlocking the Gain */ | uint32_t fagc_lmt_final_settling_steps; /* adi,fagc-lmt-final-settling-steps */ |
| uint32_t fagc_gain_index_type_after_exit_rx_mode; /* adi,fagc-gain-index-type-after-exit-rx-mode */ | uint32_t fagc_final_overrange_count; /* adi,fagc-final-overrange-count */ |
| uint8_t fagc_use_last_lock_level_for_set_gain_en; /* adi,fagc-use-last-lock-level-for-set-gain-enable */ | /* Fast AGC - Final Power Test */ |
| uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable */ | uint8_t fagc_gain_increase_after_gain_lock_en; /* adi,fagc-gain-increase-after-gain-lock-enable */ |
| uint32_t fagc_optimized_gain_offset; /* adi,fagc-optimized-gain-offset */ | /* Fast AGC - Unlocking the Gain */ |
| uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll; /* adi,fagc-rst-gla-stronger-sig-thresh-above-ll */ | uint32_t fagc_gain_index_type_after_exit_rx_mode; /* adi,fagc-gain-index-type-after-exit-rx-mode */ |
| uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable */ | uint8_t fagc_use_last_lock_level_for_set_gain_en; /* adi,fagc-use-last-lock-level-for-set-gain-enable */ |
| uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en; /* adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable */ | uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable */ |
| uint32_t fagc_rst_gla_engergy_lost_sig_thresh_below_ll; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll */ | uint32_t fagc_optimized_gain_offset; /* adi,fagc-optimized-gain-offset */ |
| uint32_t fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt */ | uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll; /* adi,fagc-rst-gla-stronger-sig-thresh-above-ll */ |
| uint8_t fagc_rst_gla_large_adc_overload_en; /* adi,fagc-rst-gla-large-adc-overload-enable */ | uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable */ |
| uint8_t fagc_rst_gla_large_lmt_overload_en; /* adi,fagc-rst-gla-large-lmt-overload-enable */ | uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en; /* adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable */ |
| uint8_t fagc_rst_gla_en_agc_pulled_high_en; /* adi,fagc-rst-gla-en-agc-pulled-high-enable */ | uint32_t fagc_rst_gla_engergy_lost_sig_thresh_below_ll; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll */ |
| uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode; /* adi,fagc-rst-gla-if-en-agc-pulled-high-mode */ | uint32_t fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt */ |
| uint32_t fagc_power_measurement_duration_in_state5; /* adi,fagc-power-measurement-duration-in-state5 */ | uint8_t fagc_rst_gla_large_adc_overload_en; /* adi,fagc-rst-gla-large-adc-overload-enable */ |
| /* RSSI Control */ | uint8_t fagc_rst_gla_large_lmt_overload_en; /* adi,fagc-rst-gla-large-lmt-overload-enable */ |
| uint32_t rssi_delay; /* adi,rssi-delay */ | uint8_t fagc_rst_gla_en_agc_pulled_high_en; /* adi,fagc-rst-gla-en-agc-pulled-high-enable */ |
| uint32_t rssi_duration; /* adi,rssi-duration */ | uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode; /* adi,fagc-rst-gla-if-en-agc-pulled-high-mode */ |
| uint8_t rssi_restart_mode; /* adi,rssi-restart-mode */ | uint32_t fagc_power_measurement_duration_in_state5; /* adi,fagc-power-measurement-duration-in-state5 */ |
| uint8_t rssi_unit_is_rx_samples_enable; /* adi,rssi-unit-is-rx-samples-enable */ | /* RSSI Control */ |
| uint32_t rssi_wait; /* adi,rssi-wait */ | uint32_t rssi_delay; /* adi,rssi-delay */ |
| /* Aux ADC Control */ | uint32_t rssi_duration; /* adi,rssi-duration */ |
| uint32_t aux_adc_decimation; /* adi,aux-adc-decimation */ | uint8_t rssi_restart_mode; /* adi,rssi-restart-mode */ |
| uint32_t aux_adc_rate; /* adi,aux-adc-rate */ | uint8_t rssi_unit_is_rx_samples_enable; /* adi,rssi-unit-is-rx-samples-enable */ |
| /* AuxDAC Control */ | uint32_t rssi_wait; /* adi,rssi-wait */ |
| uint8_t aux_dac_manual_mode_enable; /* adi,aux-dac-manual-mode-enable */ | /* Aux ADC Control */ |
| uint32_t aux_dac1_default_value_mV; /* adi,aux-dac1-default-value-mV */ | uint32_t aux_adc_decimation; /* adi,aux-adc-decimation */ |
| uint8_t aux_dac1_active_in_rx_enable; /* adi,aux-dac1-active-in-rx-enable */ | uint32_t aux_adc_rate; /* adi,aux-adc-rate */ |
| uint8_t aux_dac1_active_in_tx_enable; /* adi,aux-dac1-active-in-tx-enable */ | /* AuxDAC Control */ |
| uint8_t aux_dac1_active_in_alert_enable; /* adi,aux-dac1-active-in-alert-enable */ | uint8_t aux_dac_manual_mode_enable; /* adi,aux-dac-manual-mode-enable */ |
| uint32_t aux_dac1_rx_delay_us; /* adi,aux-dac1-rx-delay-us */ | uint32_t aux_dac1_default_value_mV; /* adi,aux-dac1-default-value-mV */ |
| uint32_t aux_dac1_tx_delay_us; /* adi,aux-dac1-tx-delay-us */ | uint8_t aux_dac1_active_in_rx_enable; /* adi,aux-dac1-active-in-rx-enable */ |
| uint32_t aux_dac2_default_value_mV; /* adi,aux-dac2-default-value-mV */ | uint8_t aux_dac1_active_in_tx_enable; /* adi,aux-dac1-active-in-tx-enable */ |
| uint8_t aux_dac2_active_in_rx_enable; /* adi,aux-dac2-active-in-rx-enable */ | uint8_t aux_dac1_active_in_alert_enable; /* adi,aux-dac1-active-in-alert-enable */ |
| uint8_t aux_dac2_active_in_tx_enable; /* adi,aux-dac2-active-in-tx-enable */ | uint32_t aux_dac1_rx_delay_us; /* adi,aux-dac1-rx-delay-us */ |
| uint8_t aux_dac2_active_in_alert_enable; /* adi,aux-dac2-active-in-alert-enable */ | uint32_t aux_dac1_tx_delay_us; /* adi,aux-dac1-tx-delay-us */ |
| uint32_t aux_dac2_rx_delay_us; /* adi,aux-dac2-rx-delay-us */ | uint32_t aux_dac2_default_value_mV; /* adi,aux-dac2-default-value-mV */ |
| uint32_t aux_dac2_tx_delay_us; /* adi,aux-dac2-tx-delay-us */ | uint8_t aux_dac2_active_in_rx_enable; /* adi,aux-dac2-active-in-rx-enable */ |
| /* Temperature Sensor Control */ | uint8_t aux_dac2_active_in_tx_enable; /* adi,aux-dac2-active-in-tx-enable */ |
| uint32_t temp_sense_decimation; /* adi,temp-sense-decimation */ | uint8_t aux_dac2_active_in_alert_enable; /* adi,aux-dac2-active-in-alert-enable */ |
| uint16_t temp_sense_measurement_interval_ms; /* adi,temp-sense-measurement-interval-ms */ | uint32_t aux_dac2_rx_delay_us; /* adi,aux-dac2-rx-delay-us */ |
| int8_t temp_sense_offset_signed; /* adi,temp-sense-offset-signed */ | uint32_t aux_dac2_tx_delay_us; /* adi,aux-dac2-tx-delay-us */ |
| uint8_t temp_sense_periodic_measurement_enable; /* adi,temp-sense-periodic-measurement-enable */ | /* Temperature Sensor Control */ |
| /* Control Out Setup */ | uint32_t temp_sense_decimation; /* adi,temp-sense-decimation */ |
| uint8_t ctrl_outs_enable_mask; /* adi,ctrl-outs-enable-mask */ | uint16_t temp_sense_measurement_interval_ms; /* adi,temp-sense-measurement-interval-ms */ |
| uint8_t ctrl_outs_index; /* adi,ctrl-outs-index */ | int8_t temp_sense_offset_signed; /* adi,temp-sense-offset-signed */ |
| /* External LNA Control */ | uint8_t temp_sense_periodic_measurement_enable; /* adi,temp-sense-periodic-measurement-enable */ |
| uint32_t elna_settling_delay_ns; /* adi,elna-settling-delay-ns */ | /* Control Out Setup */ |
| uint32_t elna_gain_mdB; /* adi,elna-gain-mdB */ | uint8_t ctrl_outs_enable_mask; /* adi,ctrl-outs-enable-mask */ |
| uint32_t elna_bypass_loss_mdB; /* adi,elna-bypass-loss-mdB */ | uint8_t ctrl_outs_index; /* adi,ctrl-outs-index */ |
| uint8_t elna_rx1_gpo0_control_enable; /* adi,elna-rx1-gpo0-control-enable */ | /* External LNA Control */ |
| uint8_t elna_rx2_gpo1_control_enable; /* adi,elna-rx2-gpo1-control-enable */ | uint32_t elna_settling_delay_ns; /* adi,elna-settling-delay-ns */ |
| /* Digital Interface Control */ | uint32_t elna_gain_mdB; /* adi,elna-gain-mdB */ |
| uint8_t pp_tx_swap_enable; /* adi,pp-tx-swap-enable */ | uint32_t elna_bypass_loss_mdB; /* adi,elna-bypass-loss-mdB */ |
| uint8_t pp_rx_swap_enable; /* adi,pp-rx-swap-enable */ | uint8_t elna_rx1_gpo0_control_enable; /* adi,elna-rx1-gpo0-control-enable */ |
| uint8_t tx_channel_swap_enable; /* adi,tx-channel-swap-enable */ | uint8_t elna_rx2_gpo1_control_enable; /* adi,elna-rx2-gpo1-control-enable */ |
| uint8_t rx_channel_swap_enable; /* adi,rx-channel-swap-enable */ | uint8_t elna_gaintable_all_index_enable; /* adi,elna-gaintable-all-index-enable */ |
| uint8_t rx_frame_pulse_mode_enable; /* adi,rx-frame-pulse-mode-enable */ | /* Digital Interface Control */ |
| uint8_t two_t_two_r_timing_enable; /* adi,2t2r-timing-enable */ | uint8_t digital_interface_tune_skip_mode; /* adi,digital-interface-tune-skip-mode */ |
| uint8_t invert_data_bus_enable; /* adi,invert-data-bus-enable */ | uint8_t digital_interface_tune_fir_disable; /* adi,digital-interface-tune-fir-disable */ |
| uint8_t invert_data_clk_enable; /* adi,invert-data-clk-enable */ | uint8_t pp_tx_swap_enable; /* adi,pp-tx-swap-enable */ |
| uint8_t fdd_alt_word_order_enable; /* adi,fdd-alt-word-order-enable */ | uint8_t pp_rx_swap_enable; /* adi,pp-rx-swap-enable */ |
| uint8_t invert_rx_frame_enable; /* adi,invert-rx-frame-enable */ | uint8_t tx_channel_swap_enable; /* adi,tx-channel-swap-enable */ |
| uint8_t fdd_rx_rate_2tx_enable; /* adi,fdd-rx-rate-2tx-enable */ | uint8_t rx_channel_swap_enable; /* adi,rx-channel-swap-enable */ |
| uint8_t swap_ports_enable; /* adi,swap-ports-enable */ | uint8_t rx_frame_pulse_mode_enable; /* adi,rx-frame-pulse-mode-enable */ |
| uint8_t single_data_rate_enable; /* adi,single-data-rate-enable */ | uint8_t two_t_two_r_timing_enable; /* adi,2t2r-timing-enable */ |
| uint8_t lvds_mode_enable; /* adi,lvds-mode-enable */ | uint8_t invert_data_bus_enable; /* adi,invert-data-bus-enable */ |
| uint8_t half_duplex_mode_enable; /* adi,half-duplex-mode-enable */ | uint8_t invert_data_clk_enable; /* adi,invert-data-clk-enable */ |
| uint8_t single_port_mode_enable; /* adi,single-port-mode-enable */ | uint8_t fdd_alt_word_order_enable; /* adi,fdd-alt-word-order-enable */ |
| uint8_t full_port_enable; /* adi,full-port-enable */ | uint8_t invert_rx_frame_enable; /* adi,invert-rx-frame-enable */ |
| uint8_t full_duplex_swap_bits_enable; /* adi,full-duplex-swap-bits-enable */ | uint8_t fdd_rx_rate_2tx_enable; /* adi,fdd-rx-rate-2tx-enable */ |
| uint32_t delay_rx_data; /* adi,delay-rx-data */ | uint8_t swap_ports_enable; /* adi,swap-ports-enable */ |
| uint32_t rx_data_clock_delay; /* adi,rx-data-clock-delay */ | uint8_t single_data_rate_enable; /* adi,single-data-rate-enable */ |
| uint32_t rx_data_delay; /* adi,rx-data-delay */ | uint8_t lvds_mode_enable; /* adi,lvds-mode-enable */ |
| uint32_t tx_fb_clock_delay; /* adi,tx-fb-clock-delay */ | uint8_t half_duplex_mode_enable; /* adi,half-duplex-mode-enable */ |
| uint32_t tx_data_delay; /* adi,tx-data-delay */ | uint8_t single_port_mode_enable; /* adi,single-port-mode-enable */ |
| uint32_t lvds_bias_mV; /* adi,lvds-bias-mV */ | uint8_t full_port_enable; /* adi,full-port-enable */ |
| uint8_t lvds_rx_onchip_termination_enable; /* adi,lvds-rx-onchip-termination-enable */ | uint8_t full_duplex_swap_bits_enable; /* adi,full-duplex-swap-bits-enable */ |
| uint8_t rx1rx2_phase_inversion_en; /* adi,rx1-rx2-phase-inversion-enable */ | uint32_t delay_rx_data; /* adi,delay-rx-data */ |
| /* Tx Monitor Control */ | uint32_t rx_data_clock_delay; /* adi,rx-data-clock-delay */ |
| uint32_t low_high_gain_threshold_mdB; /* adi,txmon-low-high-thresh */ | uint32_t rx_data_delay; /* adi,rx-data-delay */ |
| uint32_t low_gain_dB; /* adi,txmon-low-gain */ | uint32_t tx_fb_clock_delay; /* adi,tx-fb-clock-delay */ |
| uint32_t high_gain_dB; /* adi,txmon-high-gain */ | uint32_t tx_data_delay; /* adi,tx-data-delay */ |
| uint8_t tx_mon_track_en; /* adi,txmon-dc-tracking-enable */ | uint32_t lvds_bias_mV; /* adi,lvds-bias-mV */ |
| uint8_t one_shot_mode_en; /* adi,txmon-one-shot-mode-enable */ | uint8_t lvds_rx_onchip_termination_enable; /* adi,lvds-rx-onchip-termination-enable */ |
| uint32_t tx_mon_delay; /* adi,txmon-delay */ | uint8_t rx1rx2_phase_inversion_en; /* adi,rx1-rx2-phase-inversion-enable */ |
| uint32_t tx_mon_duration; /* adi,txmon-duration */ | uint8_t lvds_invert1_control; /* adi,lvds-invert1-control */ |
| uint32_t tx1_mon_front_end_gain; /* adi,txmon-1-front-end-gain */ | uint8_t lvds_invert2_control; /* adi,lvds-invert2-control */ |
| uint32_t tx2_mon_front_end_gain; /* adi,txmon-2-front-end-gain */ | /* GPO Control */ |
| uint32_t tx1_mon_lo_cm; /* adi,txmon-1-lo-cm */ | uint8_t gpo0_inactive_state_high_enable; /* adi,gpo0-inactive-state-high-enable */ |
| uint32_t tx2_mon_lo_cm; /* adi,txmon-2-lo-cm */ | uint8_t gpo1_inactive_state_high_enable; /* adi,gpo1-inactive-state-high-enable */ |
| /* GPIO definitions */ | uint8_t gpo2_inactive_state_high_enable; /* adi,gpo2-inactive-state-high-enable */ |
| int32_t gpio_resetb; /* reset-gpios */ | uint8_t gpo3_inactive_state_high_enable; /* adi,gpo3-inactive-state-high-enable */ |
| /* MCS Sync */ | uint8_t gpo0_slave_rx_enable; /* adi,gpo0-slave-rx-enable */ |
| int32_t gpio_sync; /* sync-gpios */ | uint8_t gpo0_slave_tx_enable; /* adi,gpo0-slave-tx-enable */ |
| int32_t gpio_cal_sw1; /* cal-sw1-gpios */ | uint8_t gpo1_slave_rx_enable; /* adi,gpo1-slave-rx-enable */ |
| int32_t gpio_cal_sw2; /* cal-sw2-gpios */ | uint8_t gpo1_slave_tx_enable; /* adi,gpo1-slave-tx-enable */ |
| }AD9361_InitParam; | uint8_t gpo2_slave_rx_enable; /* adi,gpo2-slave-rx-enable */ |
| | uint8_t gpo2_slave_tx_enable; /* adi,gpo2-slave-tx-enable */ |
| | uint8_t gpo3_slave_rx_enable; /* adi,gpo3-slave-rx-enable */ |
| | uint8_t gpo3_slave_tx_enable; /* adi,gpo3-slave-tx-enable */ |
| | uint8_t gpo0_rx_delay_us; /* adi,gpo0-rx-delay-us */ |
| | uint8_t gpo0_tx_delay_us; /* adi,gpo0-tx-delay-us */ |
| | uint8_t gpo1_rx_delay_us; /* adi,gpo1-rx-delay-us */ |
| | uint8_t gpo1_tx_delay_us; /* adi,gpo1-tx-delay-us */ |
| | uint8_t gpo2_rx_delay_us; /* adi,gpo2-rx-delay-us */ |
| | uint8_t gpo2_tx_delay_us; /* adi,gpo2-tx-delay-us */ |
| | uint8_t gpo3_rx_delay_us; /* adi,gpo3-rx-delay-us */ |
| | uint8_t gpo3_tx_delay_us; /* adi,gpo3-tx-delay-us */ |
| | /* Tx Monitor Control */ |
| | uint32_t low_high_gain_threshold_mdB; /* adi,txmon-low-high-thresh */ |
| | uint32_t low_gain_dB; /* adi,txmon-low-gain */ |
| | uint32_t high_gain_dB; /* adi,txmon-high-gain */ |
| | uint8_t tx_mon_track_en; /* adi,txmon-dc-tracking-enable */ |
| | uint8_t one_shot_mode_en; /* adi,txmon-one-shot-mode-enable */ |
| | uint32_t tx_mon_delay; /* adi,txmon-delay */ |
| | uint32_t tx_mon_duration; /* adi,txmon-duration */ |
| | uint32_t tx1_mon_front_end_gain; /* adi,txmon-1-front-end-gain */ |
| | uint32_t tx2_mon_front_end_gain; /* adi,txmon-2-front-end-gain */ |
| | uint32_t tx1_mon_lo_cm; /* adi,txmon-1-lo-cm */ |
| | uint32_t tx2_mon_lo_cm; /* adi,txmon-2-lo-cm */ |
| | /* GPIO definitions */ |
| | int32_t gpio_resetb; /* reset-gpios */ |
| | /* MCS Sync */ |
| | int32_t gpio_sync; /* sync-gpios */ |
| | int32_t gpio_cal_sw1; /* cal-sw1-gpios */ |
| | int32_t gpio_cal_sw2; /* cal-sw2-gpios */ |
| | /* External LO clocks */ |
| | uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv); |
| | int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, uint32_t rate); |
| | int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, uint32_t rate); |
| | }AD9361_InitParam; |
| </code> | </code> |
| |
| ==== AD9361 Doxygen Documentation ==== | ==== AD9361 Doxygen Documentation ==== |
| |
| http://analogdevicesinc.github.io/ad9361/ | http://analogdevicesinc.github.io/no-OS/ |
| |
| ===== Generic Platform ===== | ===== Generic Platform ===== |
| ==== Code Size Information ==== | ==== Code Size Information ==== |
| |
| The following information was obtained compiling the AD9361 project (with the Generic Platform Driver integrated) using the xilinx-2012.03-79-arm-xilinx-linux-gnueabi and the //Optimize for size (-Os)// option enabled. | The following information was obtained compiling the AD9361 project (with the Generic Platform Driver integrated) using the gcc v4.7.2 and the //Optimize for size (-Os)// option enabled. |
| |
| text data bss dec hex filename | text data bss dec hex filename |
| 39514 3256 8 42778 a71a ad9361.elf | 45159 1624 24 46807 b6d7 ad9361_generic |
| |
| Note: The source code from the GitHub SHA b7f6419ed5ab2ec67431312b814e7ac3fe8afb13 was used for calculating the code size information (https://github.com/analogdevicesinc/no-OS/tree/b7f6419ed5ab2ec67431312b814e7ac3fe8afb13/ad9361/sw). | Note: The source code from the GitHub SHA 13c1ba56164f4b63844f63e5dd596286b6faf8b3 was used for calculating the code size information (https://github.com/analogdevicesinc/no-OS/tree/13c1ba56164f4b63844f63e5dd596286b6faf8b3/ad9361/sw). |
| |
| ===== Xilinx Platform ===== | ===== Xilinx Platform ===== |
| |
| ==== Required Software ==== | ==== Required Software ==== |
| * Xilinx Vivado 2013.4 | {{page>./../../../../../resources/no-os/build}} |
| ==== Software Setup for Vivado ==== | |
| | |
| Example for a ZC702 board: | |
| * After [[http://wiki.analog.com/resources/fpga/docs/hdl#building_on_vivado | building the project in Vivado]] for the used FPGA board, a //**SDK_Export**// folder will be created in //**../fmcomms2_board.sdk/SDK**// | |
| * Open the Xilinx SDK for Vivado. When the SDK starts it asks to provide a folder where to store the workspace. Any folder can be provided. | |
| * Go to //**File->New->Application project**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_new_app_project.png?600 | New Application Project}} | |
| * Use a new hardware platform, so choose //**Create new**// in //**Hardware Platform**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_new_platform.png?400 | New Platform}} | |
| * In //**Target Hardware Specification**// browse the location of //**SDK_Export\hw\system.xml**// and click //**Finish**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_new_hw_project.png?400 | New Hardware Project}} | |
| * Then give a name to the project and click //**Next**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_project_name.png?400 | Project Name }} | |
| | |
| * In the next window choose //**Empty Application**// and click //**Finish**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_templates.png?400 | Available Templates }} | |
| * Now the project without source code looks like this | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_empty_project_zynq.png?600 | Empty Project }} | |
| | |
| * Then the source code must be added from Github to //**src**// folder(the AD9361 No-OS Software and the Xilinx Platform Driver are mandatory. The Console Commands Driver is optional). (one method to add files is to simply drag drop from source code directory to SDK Project explorer source code, or to add them in under the correct sdk project directory/src folder) | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_no_os_sdk_project.png?600 | SDK Project }} | |
| | |
| * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option. (if there's errors such as command.c #include "../ad9361_api.h" can't find it just change the library to correct path #include "ad9361_api.h") | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_project_explorer.png?600 | Project Explorer }} | |
| | |
| * On MicroBlaze platforms an additional step is required: the default Heap Size value must be increased - a new value of 0x100000 should be fine. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:ad9361_no_os_microblaze_heap_size.png |}} | |
| | |
| * To be able to use the Xilinx platform, you should uncomment //**#define XILINX_PLATFORM**// from Macros and Constants Definitions section in //main//. And if you use the console commands, then //**#define CONSOLE_COMMANDS**// should be also uncommented in //main//. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_uncomment_platform_and_commands.png?400 | Project Explorer }} | |
| | |
| * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. You can program the FPGA by going to //**Xilinx Tools**//. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_program_fpga.png?600 | Program FPGA }} | |
| * Then choose this bitstream and press //**Program**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_program_fpga_with_bitstream.png?400 | Program FPGA with bitstream}} | |
| * This window will appear next. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_program_fpga_progress.png?400 | Program FPGA progress}} | |
| * Afterwards a //Run Configuration// must be created and then press //**Run**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_run_configuration.png?600 | Run Configuration}} | |
| | |
| | |
| | |
| * The output of the example program can be viewed in the SDK console by enabling the //Connect STDIO Console// option and setting the baud rate of the UART port to 115200. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:software:fmcomms2_stdio_config_vivado.png?600 | STDIO configuration }} | |
| | |
| As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must be used in the UART terminal: | |
| * Baud Rate: 115200bps | |
| * Data: 8 bit | |
| * Parity: None | |
| * Stop bits: 1 bit | |
| * Flow Control: none | |
| | |
| After running the example program the system is configured to generate a sinewave on each of the 2 channels and send it over the air using a 2.4GHz carrier. The signal is received back, brought to baseband again and digitized by the 2 ADCs(one for each channel) on the FMCOMMS2. The I and Q samples generated by the ADCs can be viewed using the //Vivado Hardware Manager//. These are the steps than need to be followed to view the sine waves: | |
| | |
| * First make sure that the board is programmed and the program is currently running | |
| * Then open Vivado and go to //**Flow->Open Hardware Manager**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_open_hadware_manager.png?600 | Open Hardware Manager}} | |
| * In the new window select //**Open a new hardware target**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_open_new_hardware_target.png | |
| ?600 | Open New Hardware Target}} | |
| * Then click //**Next**// 4 times and then //**Finish**// | |
| | |
| {{:resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_open_new_hardaware_target_start.png?290| Open New Hardware Target}}{{:resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_open_new_hardaware_target_server_name.png?290| Server name}}{{:resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_open_new_hardware_target_select_target.png | |
| ?290| Select Target}} | |
| {{:resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_open_new_hardware_target_set_properties.png?290| Set Properties}}{{:resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_open_new_hardware_target_finish.png?290| Open New Hardware Target}} | |
| \\ | |
| * This is how the //Vivado Hardware Manager// looks like. Now go to Probes file. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hardware_device_properties.png?600 | Device Properties}} | |
| * And browse for the folder where the project was complied //**../fmcomms2_board.runs/impl_1/debug_nets.ltx**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_specify_probes_file.png?600 | Specify Probes File}} | |
| * Then do a right click on the active target and choose //**Refresh Device**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_refresh_device.png?600 | Refresh Device}} | |
| * Afterwards do another right click on the active target and choose //**Run Trigger**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_run_trigger.png?600 | Run Trigger}} | |
| * This is how the 48 digital signals look like. Now we have to compose the sinewaves. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_ila_signals.png?600 | ILA Signals}} | |
| * First select the first 12 signals, do a right click and choose //**New Virtual Bus**// | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_ila_signals_new_virtual_bus.png?600 | New Virtual Bus}} | |
| * Then give a name to that virtual bus | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_ila_signals_new_virtual_bus_specify_name.png?600 | Specify Virtual Bus Name}} | |
| * In order to see a sinewave you have to right click on the name of the virtual bus, choose //**Analog**// for //**Waveform Style**// option. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_ila_signales_waveform_style_analog.png?600 | Analog Waveform Style}} | |
| * Now you can see a sinewave, but the radix is not the good one. In order to have the right radix, you must choose //**Signed Decimal**// for //**Radix**//. | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_ila_signals_radix_signed_decimal.png?600 | Signed Decimal Radix}} | |
| * Now the signal looks like a sinewave | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_ila_signals_one_virtual_bus_forms_a_sinewave.png?600 | One Virtual Bus Sinewave}} | |
| * And after you did the same steps for the other 3x12 remaining signals, you should have 4 sinewaves composed of 48 signals. ON FMCOMMS2 there are 2 channels, each channel with 2 signals (I and Q). | |
| {{ :resources:eval:user-guides:ad-fmcomms2-ebz:hardware:fmcomms2_vivado_hw_ila_signals_4_virtual_buses_form_sinewaves.png?600 | 4 Virtual Buses Sinewaves}} | |
| |
| ==== Console Commands Driver ==== | ==== Console Commands Driver ==== |
| |
| <WRAP round download 90%> | <WRAP round download 90%> |
| * **AD9361 No-OS Software** https://github.com/analogdevicesinc/no-OS/tree/2014_R1/ad9361/sw | * **AD9361 No-OS Software** https://github.com/analogdevicesinc/no-OS/tree/master/ad9361/sw |
| * **Generic Platform Driver** https://github.com/analogdevicesinc/no-OS/tree/2014_R1/ad9361/sw/platform_generic | * **Generic Platform Driver** https://github.com/analogdevicesinc/no-OS/tree/master/ad9361/sw/platform_generic |
| * **Linux Userspace Platform Driver** https://github.com/analogdevicesinc/no-OS/tree/2014_R1/ad9361/sw/platform_linux | * **Linux Userspace Platform Driver** https://github.com/analogdevicesinc/no-OS/tree/master/ad9361/sw/platform_linux |
| * **Xilinx Platform Driver** https://github.com/analogdevicesinc/no-OS/tree/2014_R1/ad9361/sw/platform_xilinx | * **Xilinx Platform Driver** https://github.com/analogdevicesinc/no-OS/tree/master/ad9361/sw/platform_xilinx |
| * **Xilinx Scripts** https://github.com/analogdevicesinc/no-OS/tree/2014_R1/ad9361/scripts | * **Xilinx Scripts** https://github.com/analogdevicesinc/no-OS/tree/master/ad9361/scripts |
| * **Console Commands Driver** https://github.com/analogdevicesinc/no-OS/tree/2014_R1/ad9361/sw/console_commands | * **Console Commands Driver** https://github.com/analogdevicesinc/no-OS/tree/master/ad9361/sw/console_commands |
| </WRAP> | </WRAP> |
| |
| <WRAP round download 90%> | <WRAP round download 90%> |
| |
| * **ZED HDL Reference Design for Vivado: ** https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms2/zed | * **ZED HDL Reference Design for Vivado: ** https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms2/zed |
| * **ZC702 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms2/zc702 | * **ZC702 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms2/zc702 |
| * **ZC706 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms2/zc706 | * **ZC706 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms2/zc706 |
| * **AC701 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms2/ac701 | * **KC705 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms2/kc705 |
| * **KC705 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms2/kc705 | * **VC707 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms2/vc707 |
| * **VC707 HDL Reference Design for Vivado: **https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms2/vc707 | |
| | |
| * **ML605 HDL Reference Design for ISE: ** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_ad9361_ml605 | |
| </WRAP> | </WRAP> |
| |
| <WRAP round download 90%> | <WRAP round download 90%> |
| * **ZC702 HDL Reference Design for Vivado: | * **ZC702 HDL Reference Design for Vivado: |
| **https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms5/zc702 | **https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms5/zc702 |
| * **ZC706 HDL Reference Design for Vivado: | * **ZC706 HDL Reference Design for Vivado: |
| **https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms5/zc706 | **https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms5/zc706 |
| |
| </WRAP> | </WRAP> |
