This version is outdated by a newer approved version.
This version (24 Sep 2014 21:00) was approved by Robin Getz.The Previously approved version (11 Jun 2014 15:39) is available.
This version (24 Sep 2014 21:00) was approved by Robin Getz.The Previously approved version (11 Jun 2014 15:39) is available.This is an old revision of the document!
Table of Contents
AD-FMCOMMS2-EBZ / AD-FMCOMMS3-EBZ / AD-FMCOMMS4-EBZ HDL / AD-FMCOMMS5-EBZ HDL Reference Design
Functional Overview
The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given below. The device interface is a self-contained peripheral similar to other such pcores in the system. The core is programmable through an AXI-lite interface. The data path consists of a VDMA and DMA interface for the transmit and receive path respectively.
Digital Interface
The digital interface consists of 12bits of DDR data and supports full duplex operation in all configurations up to 2×2. The transmit and receive data paths share a single clock. The data is sent or received based on the configuration (programmable) from separate transmit and to separate receive chains.
Transmit
In the transmit direction, complex I and Q signals are generated for each RF. The digital source could either be an internal DDS or from the external DDR via VDMA. The internal DDS phase and frequency are programmable.
Receive
In the receive direction, each component of the delineated data is passed to a PN monitor. The monitors validates the digital interface signal capture and timing. The data then optionally DC-filtered, corrected for I/Q offset and phase mismatches and is written to the external DDR memory via DMA. An optional off-line FFT core may be used to generate a spectrum plot.
Control and SPI
The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.
Supported Devices
Supported Carriers
These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done.
Our recommended plaforms are the Zynq based systems:
but it also works on the fabric only solutions (for experts, who have used the zynq based systems in the past).
Download
FPGA Reference Designs on GitHub :
- Vivado Downloads
- https://github.com/analogdevicesinc/hdl (This is our main repository and contents change frequently. A release (more stable) branch will be available soon.)
- XPS/EDK Downloads
- Previous Releases & Tags
- Git Repository
- Questions? Ask Help & Support.
Generating Xilinx netlist files
The repository will not contain Xilinx netlist files, only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.
Navigation - AD-FMCOMMS2-EBZ
resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl.1411585222.txt.gz · Last modified: 24 Sep 2014 21:00 by Robin Getz