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resources:eval:user-guides:ad-fmcomms11-ebz:reference_hdl [10 Jun 2019 10:14] – [Data Link Layer] Update with lane remapping Istvan Csomortaniresources:eval:user-guides:ad-fmcomms11-ebz:reference_hdl [14 Jan 2021 05:11] (current) – user interwiki links Robin Getz
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 ===== Functional Overview ===== ===== Functional Overview =====
  
-The HDL reference design is an embedded system built around a processor core either ARM, NIOS-II or Microblaze. A functional block diagram of the system is shown below. The high speed digital interface of the converters is handled by the [[https://wiki.analog.com/resources/fpga/peripherals/jesd204|JESD204B framework]]. Due to the system's memory interface bandwidth limitation, there are intermediary buffers in the both TX and RX data paths, in order to save and push data using high data rates. In case of the ZC706 carrier board, the RX buffer depth is 1Gbyte, and TX buffer depth is 1Mbyte. This depths can be swapped if required.+The HDL reference design is an embedded system built around a processor core either ARM, NIOS-II or Microblaze. A functional block diagram of the system is shown below. The high speed digital interface of the converters is handled by the [[/resources/fpga/peripherals/jesd204|JESD204B framework]]. Due to the system's memory interface bandwidth limitation, there are intermediary buffers in the both TX and RX data paths, in order to save and push data using high data rates. In case of the ZC706 carrier board, the RX buffer depth is 1Gbyte, and TX buffer depth is 1Mbyte. This depths can be swapped if required.
  
 By default the AD9162 is configured in complex mode with 8 lanes (see Table 16. in data sheet), and the AD9625 is configured in generic operation mode with 8 lanes (see Table 16. in data sheet). Both JESD204 interfaces run in Subclass 0. By default the AD9162 is configured in complex mode with 8 lanes (see Table 16. in data sheet), and the AD9625 is configured in generic operation mode with 8 lanes (see Table 16. in data sheet). Both JESD204 interfaces run in Subclass 0.
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 The IP is equivalent with the Xilinx licensed JESD204 IP.  The IP is equivalent with the Xilinx licensed JESD204 IP. 
  
-To relax the constraints for PCB design, the n-th physical lane it's not connected to the n-th logical lane, therefor there is a remapping scheme between the physical and link layer to reorder the data streams. In case of the FMCOMMS11 board, both ADC and DAC side using the same remapping scheme. +To relax the constraints for PCB design, the n-th physical lane it's not connected to the n-th logical lane, therefor there is a remapping scheme between the physical and link layer to reorder the data streams. In case of the FMCOMMS11 board, both ADC and DAC side using the same remapping scheme. With the following remapping scheme: {0 1 2 3 7 4 6 5}, where the n-th logical lane is mapped to the "list[n]" physical lane.
  
 <code tcl> <code tcl>
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 ==== Constraints ==== ==== Constraints ====
  
-As shown below, the transceiver channels are connected to the appropriate high speed FMC lane. The lane remapping is done after the JESD204 link layer, with the following remapping scheme: {0 1 2 3 7 4 6 5}, where the n-th logical lane is mapped to the "list[n]" physical lane. +As shown below, the transceiver channels are connected to the appropriate high speed FMC lane. The lane remapping is done after the JESD204 link layer, see the **Data Link Layer** section for more details.  
  
 <code xdc> <code xdc>
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 ===== Building the HDL Project ===== ===== Building the HDL Project =====
  
-When building the project, you should always use the recommended version of the tools for the specific [[https://wiki.analog.com/resources/fpga/docs/releases | release]]. In this example, we'll use release 2019_r1, which has Vivado 2018.3 as the recommended version. If you're using different Vivado versions, it's possible that there are slight modifications on how the synthesis works, or different Xilinx IP changes, which affect the system functionality.+When building the project, you should always use the recommended version of the tools for the specific [[/resources/fpga/docs/releases | release]]. In this example, we'll use release 2019_r1, which has Vivado 2018.3 as the recommended version. If you're using different Vivado versions, it's possible that there are slight modifications on how the synthesis works, or different Xilinx IP changes, which affect the system functionality.
  
 <code> <code>
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 <WRAP round help 80%> <WRAP round help 80%>
 **Questions?** Feel free to ask your questions in EngineerZone support forums. **Questions?** Feel free to ask your questions in EngineerZone support forums.
-  * [[https://ez.analog.com/community/fpga|FPGA Reference Design]]+  * [[ez>community/fpga|FPGA Reference Design]]
 </WRAP> </WRAP>
 ===== References ===== ===== References =====
resources/eval/user-guides/ad-fmcomms11-ebz/reference_hdl.txt · Last modified: 14 Jan 2021 05:11 by Robin Getz

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