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resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:no_os_microblaze [28 Aug 2013 15:30] – [Hardware Setup] rejeesh kuttyresources:eval:user-guides:ad-fmcomms1-ebz:quickstart:no_os_microblaze [22 Nov 2021 14:31] (current) – Stefan-Robert Raus
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-====== AD-FMCOMMS1-EBZ Quick Start Guide on Xilinx FPGA Boards Without OS ======+ ====== AD-FMCOMMS1-EBZ Quick Start Guide on Xilinx FPGA Boards Without OS ====== 
 + 
 +{{page>/wiki/common#retired&nofooter&noheader}}
  
 This guide provides some quick instructions on how to setup the AD-FMCOMMS1-EBZ on either: This guide provides some quick instructions on how to setup the AD-FMCOMMS1-EBZ on either:
-  * [[xilinx>ML605]] + 
-  * [[xilinx>KC705]] +  * [[xilinx>AC701]]  
-  * [[xilinx>ZC702]] +  * [[xilinx>KC705]]  
-  * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1028&Prod=ZEDBOARD|Digilent ZED Board]] +  * [[xilinx>VC707]]  
-===== Required Software ===== +  * [[xilinx>ZC702]]  
-  * Xilinx Software Development Kit 14.4+  * [[xilinx>ZC706]]  
 +  * [[http://zedboard.org/product/zedboard/|Avnet ZED Board]] 
 + 
 +<WRAP round important 80%> 
 +\\ 
 +The ML605 XPS project remain on this website only for legacy purposes. The support for XPS projects has been discontinued.  
 +</WRAP> 
 + 
 +==== Required Software ==== 
 +  * We upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/tree/master | git repository ]].  
 + 
 +==== Required Hardware ==== 
 +  * AD-FMCOMMS1-EBZ FMC Board 
 +  * Xilinx ML605 / Xilinx AC701 / Xilinx KC705 / Xilinx VC707 / Xilinx ZC702 / Xilinx ZC706 / Digilent ZED
  
 ===== Downloads =====   ===== Downloads =====  
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 <WRAP round download 80%> <WRAP round download 80%>
 **no-OS Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/fmcomms1 \\ **no-OS Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/fmcomms1 \\
-**ML605 HDL Reference Design: ** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_xcomm \\ +\\ 
-**KC705 HDL Reference Design: ** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_xcomm_kc705\\ +**ML605 HDL Reference Design for ISE: ** 
-**ZC702 HDL Reference Design: ** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_xcomm_zc702\\ +https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_xcomm\\ 
-**ZED HDL Reference Design: ** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_xcomm_zed+\\ 
 + 
 +**Latest release for Vivado** 
 +  
 +**AC701: ** 
 +https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms1/ac701\\ 
 +**KC705: **  
 +https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms1/kc705\\ 
 +**VC707: ** 
 +https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms1/vc707\\ 
 +**ZC702: ** 
 +https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms1/zc702\\ 
 +**ZC706: ** 
 +https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms1/zc706\\ 
 +**ZED: ** 
 +https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms1/zed\\ 
 + 
 +**Old releases for Vivado**\\ 
 + 
 +**For Vivado 2013.4 :**https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r1/projects/fmcomms1/
 </WRAP> </WRAP>
-===== Required Hardware ===== +
-  * Xilinx ML605 / Xilinx KC705 / Xilinx ZC702 / Digilent ZED Board +
-  * AD-FMCOMMS1-EBZ FMC Board+
  
 ===== Hardware Setup ===== ===== Hardware Setup =====
   * Connect the power and UART cables of the Xilinx FPGA board   * Connect the power and UART cables of the Xilinx FPGA board
-  * Connect the AD-FMCOMMS1-EBZ FMC board to the Xilinx FPGA board on the LPC FMC connector +  * Connect the AD-FMCOMMS1-EBZ FMC board to the Xilinx FPGA board on the: 
 +    * LPC FMC connector for KC705, ZC706, ZED; 
 +    * LPC FMC1 connector for ZC702; 
 +    * HPC FMC connector for AC701, ML605; 
 +    * HPC FMC2 connector for VC707. 
  
 The transmit signal may be observed using a spectrum analyzer. The receive side may be sourced by either the transmit side or a signal source. If it is the transmit side, connect an SMA cable from the transmit to receive or connect antennae on both. If it is a signal source the frequency needs to be 2.4G__+__f, 0 dBm where f is the baseband. The transmit signal may be observed using a spectrum analyzer. The receive side may be sourced by either the transmit side or a signal source. If it is the transmit side, connect an SMA cable from the transmit to receive or connect antennae on both. If it is a signal source the frequency needs to be 2.4G__+__f, 0 dBm where f is the baseband.
  
-===== Software Setup ===== +<WRAP round info %80> 
- +The default RX gain in case of no-OS software is 10 dB. This could be too high, when an SMA cable is used for external loop-back. In this case the user should reduce the RX gain to its minimum value: 4.5 dB, in order to prevent saturation. 
-The **HDL Reference Design** for each supported Xilinx FPGA board contains a folder called //**SDK_Workspace**// which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA. +</WRAP> 
-These are the steps that need to be followed to recreate the software project: +===== Software Setup for Vivado ===== 
-  * Copy the //**SDK_Workspace**// folder on your PC. Make sure that the path where it is stored does not contain any spaces. +Example for a ZC702 board: 
-  * Copy the no-OS drivers source code to the //**SDK_Workspace/sw/src**// folder. +  * After [[/resources/fpga/docs/build | building the project in Vivado]] for the used FPGA board, a //**SDK_Export**// folder will be created in //**../fmcomms1_board.sdk/SDK**// 
-{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:src_files.png?400 | no-OS driver Source Files}} +  * Open the Xilinx SDK for Vivado. When the SDK starts it asks to provide a folder where to store the workspace. Any folder can be provided.  
-  * Open the Xilinx SDK. When the SDK starts it asks for a to provide a folder where to store the workspace. Any folder can be provided. +  * Go to //**File->New->Application project**//  
-  * In the SDK select the //**File->Import**// menu option to import the software projects into the workspace. +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:new_app_project.png?600 | New Application Project}} 
-{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:file_import.png?400 | Import Projects}} +  * Use a new hardware platform, so choose //**New**// in //**Target Hardware**// section  
-  * In the //Import// window select the //**General->Existing Projects into Workspace**// option. +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:new_platform.png?400 | New Platform}} 
-{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:existing_project_import.png?400 | Existing Projects Import}} +  * At the **Target Hardware Specification** section browse the location of the hardware description file. This file's extension should be **.xml** or **.hdf**, and is located in the directory of the hdl design. **Note:** If the file does not exist, probably you forgot to make an **Export hardware** (in Vivado **File** -> **Export** -> **Export Hardware...**) 
-  * In the //Import Projects// window select the //**SDK_Workspace**// folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //Projects// list. Press //Finish// to finalize the import process. +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_new_hw_project.png?400 | New Hardware Project}} 
-{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:projects_import.png?400 | Projects Import}}  +  * Then give a name to the project and click //**Next**// 
-  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option. +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:project_name.png?400 | Project Name }} 
-{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:project_explorer.png?400 | Project Explorer}}+  * In the next window choose //**Empty Application**// and click //**Finish**// 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:templates.png?400 | Available Templates }} 
 +  * Now the project without source code looks like this 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:empty_project_zynq.png?600 | Empty Project }} 
 +  * Then the source code(all folders from //**no-OS Drivers**//, except Chipscope, Evaluate and PIC)  must be added from Github to //**src**// folder. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_project_without_include_directories_paths.png?600 | Project without directories paths}} 
 +  * Afterwards click right on project name and go to //**Properties**// 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:project_properties.png?600 | Project properties}} 
 +  * In the window that appears go to //**Settings->Directories**// and include the paths of the directories from //**src**// for both //**Debug**// and //**Release**// configurations. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_settings_include_directories_paths.png?600 | Include paths}} 
 +  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_project_explorer_zynq.png?600 | Project Explorer}}
   * The default project configuration assumes that a Xilinx ML605 FPGA board is used and that the FMCOMMS1 is connected to this board on the FMC LPC connector. In the file //Common/main.c// change the //XCOMM_DefaultInit// initialization structure so that the FPGA board and the FMC port used to connect the FMCOMMS1 to the FPGA board correspond to your actual hardware setup.   * The default project configuration assumes that a Xilinx ML605 FPGA board is used and that the FMCOMMS1 is connected to this board on the FMC LPC connector. In the file //Common/main.c// change the //XCOMM_DefaultInit// initialization structure so that the FPGA board and the FMC port used to connect the FMCOMMS1 to the FPGA board correspond to your actual hardware setup.
 {{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:board_config.png?400 | Board Configuration}} {{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:board_config.png?400 | Board Configuration}}
-  * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system.+  * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. You can program the FPGA by going to //**Xilinx Tools**//. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_program_fpga.png?600 | Program FPGA}} 
 +  * Then choose this bitstream and press //**Program**//. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_program_fpga_with_bitstream.png?400 | Program FPGA with bitstream}} 
 +  * This window will appear next. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_program_fpga_progress.png?400 | Program FPGA progress}} 
 +  * Afterwards a //Run Configuration// must be created and then press //**Run**//. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_run_configuration.png?600 | Run Configuration}}
  
 The no-OS drivers source code contains an example on how to: The no-OS drivers source code contains an example on how to:
Line 57: Line 111:
 The example code outputs on the UART the status of each operation as shown below. The example code outputs on the UART the status of each operation as shown below.
  
-{{ :resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:xcomm_test.png?400 | XCOMM Test Program Output}}+{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:fmcomms1_test_uart.png?300 | UART Test}}
  
-The output of the example program can be viewed in the SDK console by enabling the //Connect STDIO Console// option and setting the baud rate of the UART port to 57600.+The output of the example program can be viewed in the SDK console by enabling the //Connect STDIO Console// option and setting the baud rate of the UART port to 115200.
  
-{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:stdio_config.png?400 | STDIO Configuration}}+{{ :resources:eval:user-guides:ad-fmcomms1-ebz:quickstart:stdio_config_vivado.png?600 | Baud rate}}
  
-As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must used in the UART terminal: +As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must be used in the UART terminal: 
-  * Baud Rate: 57600bps (for ML605, KC705) / 115200bps (for ZC702 and ZED Board)+  * Baud Rate: 115200bps
   * Data: 8 bit   * Data: 8 bit
   * Parity: None   * Parity: None
Line 72: Line 126:
 The example code is located in the "//Common/main.c//" file and the implementations of  the ADC and DAC test routines can be found in the "//Common/test.c//" file.  The example code is located in the "//Common/main.c//" file and the implementations of  the ADC and DAC test routines can be found in the "//Common/test.c//" file. 
  
-After running the example program the system is configured to generate a sinewave and send it over the air using a 2.4GHz carrier. The signal is received back, brought to baseband again and digitized by the ADC on the FMCOMMS1. The I and Q samples generated by the ADC can be viewed using the Chipscope project from the "//Chipscope//" folder. These are the steps than need to be followed to view the sine waves in Chipscope: +After running the example program the system is configured to generate a sinewave and send it over the air using a 2.4GHz carrier. The signal is received back, brought to baseband again and digitized by the ADC on the FMCOMMS1. The I and Q samples generated by the ADC can be viewed using the //Vivado Hardware Manager//. These are the steps than need to be followed to view the sine waves: 
-  * open Chipscope and press the **//Open Cable/Search JTAG Chain//** button (the leftmost button located under the File menu) + 
-  * open the //Chipscope/.cpj// project that corresponds to the used FPGA board +  * First make sure that the board is programmed and the program is currently running 
-  * start the data capture +  * Then open Vivado and go to //**Flow->Open Hardware manager**//  
-This is how the output of the ADC looks like.+{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_open_hardware_manager.png?600 | Open Hardware Manager}} 
 +  * In the new window select //**Open a new hardware target**// 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_open_new_hardware_target.png?600 | Open New Hardware Target}} 
 +  * Then click //**Next**// 4 times and then //**Finish**// 
 +{{:resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_open_new_hardaware_target_start.png?290| Open New Hardware Target}}{{:resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_open_new_hardaware_target_server_name.png?290| Server name}}{{:resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_open_new_hardware_target_select_target.png?290| Select Target}} 
 +{{:resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_open_new_hardware_target_set_properties.png?290| Set Properties}}{{:resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_open_new_hardware_target_finish.png?290| Open New Hardware Target}} 
 +\\ 
 +  * This is how the //Vivado Hardware Manager// looks like. Now go to Probes files. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_hardware_device_properties.png?600 | Device Properties}} 
 +  * And browse for the folder where the project was compiled //**../fmcomms1_board.runs/impl_1/debug_nets.ltx**// 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_specify_probes_file.png?400 | Specify Probes File}}   
 +  * Then do a right click on the active target and choose //**Refresh Device**// 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_hw_refresh_device.png?600 | Refresh Device}} 
 +  * Afterwards do another right click on the active target and choose //**Run Trigger**// 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:vivado_hw_run_trigger.png?600 | Run Trigger}} 
 +  * This is how the 56 digital signals look like. Now we have to compose the sinewaves. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_vivado_hw_ila_signals.png?600 | ILA Signals}} 
 +  * First select the first 14 signals, do a right click and choose //**New Virtual Bus**// 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_vivado_hw_ila_signals_new_virtual_bus.png?600 | New Virtual Bus}} 
 +  * Then give a name to that virtual bus 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_vivado_hw_ila_signals_new_virtual_bus_specify_name.png?600 | Specify Virtual Bus Name}} 
 +  * In order to see a sinewave you have to right click on the name of the virtual bus, choose //**Analog**// for //**Waveform Style**// option. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_vivado_hw_ila_signals_waveform_style_analog.png?600 | Analog Waveform Style}} 
 +  * Now you can see a sinewave, but the radix is not the good one. In order to have the right radix, you must choose //**Signed Decimal**// for //**Radix**//. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_vivado_hw_ila_signals_radix_signed_decimal.png?600 | Signed Decimal Radix}} 
 +  * Now the signal looks like a sinewave 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_vivado_hw_ila_signals_one_virtual_bus_forms_a_sinewave.png?600 | One Virtual Bus Sinewave}} 
 +  * And after you did the same steps for the other 3x14 remaining signals, you should have 4 sinewaves composed of 56 signals. Because of the working frequency of the ILA core, data has been split into 2 buses, so the actual data from the Evaluation board would be I_0 interleaved with I_1, and Q_0 interleaved with Q_1. 
 +{{ :resources:eval:user-guides:ad-fmcomms1-ebz:hardware:fmcomms1_vivado_hw_ila_signals_4_virtual_buses_form_sinewaves.png?600 | 4 Virtual Buses Sinewaves}} 
  
-{{ :resources:fpga:xilinx:fmc:ad-fmcomms1-ebz:xcomm_chipscope.png?500 | ADC output}}   
  
      
 {{navigation AD-FMCOMMS1-EBZ#zynq|Linux on ZC702, ZC706, ZED#.:|Quick Start Guides#none}} {{navigation AD-FMCOMMS1-EBZ#zynq|Linux on ZC702, ZC706, ZED#.:|Quick Start Guides#none}}
resources/eval/user-guides/ad-fmcomms1-ebz/quickstart/no_os_microblaze.1377696601.txt.gz · Last modified: 28 Aug 2013 15:30 by rejeesh kutty

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