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AD-FMCMOTCON2-EBZ Controller Board


  • Compatible with all Xilinx FPGA platforms with FMC LPC or HPC connectors
  • Digital board for interfacing with the low and high voltage drive boards
  • FMC signals voltage adaptation interface for seamless operation on all FMC voltage levels
  • Fully isolated digital control and feedback signals
    • 2 isolated GPOs
    • 2 isolated GPIs
    • 18 isolated drive signals – can drive 2 bridges with 4 legs simultaneously
    • 6 high speed ADC digital interfaces (data + clock)
  • Isolated Xilinx XADC interface
  • 2 x Gbit Ethernet PHYs for high speed industrial communication - RGMII mode
  • Single ended Hall + Differential Hall + Encoder + Resolver interfaces
    • 2 x single ended HALL, 2 x differential HALL, 2 x encoder interfaces – this allows 2 motors to be driven simultaneously
  • Digital sensors interfaces
    • EnDat
    • BISS Interface

Block Diagram

Simplified Block Diagram

Picture and Main Components


Key Parts

AD7401A 5 kV rms, isolated 2nd order Sigma-Delta modulator
ADA4084-2 30 V, Low noise, rail-to-rail I/O, low power operational amplifier
AD8646 24 MHz rail-to-rail dual op amp
AD2S1210 Variable resolution, 10-bit to 16-bit R/D converter with reference oscillator
ADuM5000 isoPower® integrated isolated dc-to-dc converter
ADP1614 1000 mA, 2.5 MHz buck-boost dc-to-dc converter
ADM660 CMOS switched-capacitor voltage converter
ADuM7640 Triple channel digital isolator
Voltage Translation
ADG3308 8-channel bidirectional level translator
ADG704 CMOS, low voltage 2.5 Ω 4-channel multiplexer
ADG759 CMOS low voltage, 3 ohms 4-channel multiplexer
High Speed Communication
88E1512 Marvell Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver

ADC FPGA Interface

The AD7403 Isolated Sigma-Delta Modulators present on the controller board have a 2 wires signal interface with the FPGA:

  • 10 / 20 MHz clock input
  • 1 bit digital data stream output

The reconstruction of the data provided by the AD7403 modulator can be done using a SINC3 filter. A filter model and HDL implementation are provided in the AD7403 datasheet. Typical filter output characteristics:

  • Output code: 16 bit
  • Sampling rate: 78kHz

The output code resolution and sampling rate can be controlled by changing the filter’s model and decimation. Polyphase interpolation filters are utilized to increase the sampling rate of the system.

Position & Speed Sensors FPGA Interface

Single digital interface for multiple position sensors

  • Single Ended HALL
  • Differential HALL
  • BEMF
  • Encoder

3 digital signals between HW and the FPGA

  • HALL A / BEMF A / Encoder Channel A
  • HALL B / BEMF B / Encoder Channel B
  • HALL C / BEMF C / Encoder Index

Sensor selection is done with jumpers on the controller board. The hardware conditions the analog signals and sends clean digital signals to the FPGA.



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resources/eval/user-guides/ad-fmcmotcon2-ebz/hardware/controller_board.1427366082.txt.gz · Last modified: 26 Mar 2015 11:34 by Andrei Cozma