This version is outdated by a newer approved version.
This version (25 Jan 2021 19:15) was approved by Robin Getz.The Previously approved version (09 Jan 2021 00:32) is available.
This version (25 Jan 2021 19:15) was approved by Robin Getz.The Previously approved version (09 Jan 2021 00:32) is available.This is an old revision of the document!
Table of Contents
Xilinx HDL Reference Design
This design is targeted for Zynq based FPGA systems. It has the complete infrastructure for Linux support.
Reference Design
The reference design contains HDL blocks for interfacing with the various components of the motor control hardware:
- ADC Interface - Implements the communication with the AD7401 sigma delta modulators present on the AD-FMCMOTCON1-EBZ and also the SINC3 filters for demodulating the 1-bit digital stream provided by these parts. This HDL block exposes a set of registers that can be accessed through the AXI Lite interface. An AXI Streaming interface connected to a DMA controller allows the block to stream real time data to the application layer.
- Controller Interface - Implements the interface to the IP control blocks in the system. An AXI Streaming interface connected to a DMA controller allows the block to stream real time data to the application layer.
- MathWorks FOC IP - The FOC controller model is provided by MathWorks and it is integrated in the HDL design as a standalone IP core. The controller model is packaged into an IP core using the Simulink Workflow Advisor. It exposes a set of AXI-Lite registers that can be used to control the IP's operation as well as a set of interface signals for encoder input, current measurement data, inverter control and internal operations monitoring. All the monitoring signals connect to the Controller Interface IP which allows these signals to be monitored from the Linux IIO Scope application. The AXI-Lite registers exposed by the controller IP core can be directly accessed through an uio driver present in the ADI Linux distribution for Zynq.
- Position & Speed Processing - Implements the algorithm for converting Hall, BEMF and Encoder signals into speed and position data. This HDL block exposes a set of registers that can be accessed through the AXI Lite interface. An AXI Streaming interface connected to a DMA controller allows the block to stream real time data to the application layer.
Vivado Design Generation
Start Vivado in GUI mode, in a Windows environment. The project is generateed using the Vivado TCL console by issuing the following commands:
- cd [project_path]/projects/motor_control/zed
- source ./system_project.tcl
This will generate the entire system and create the bit file.
Downloads
Setting up Linux
For instructions on how to setup linux on the ZED board, please follow instructions at:
Linux on Zynq Quick Start Guide
Support
- Questions? Ask Help & Support.
Navigation - AD-FMCMOTCON1-EBZ
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resources/eval/user-guides/ad-fmcmotcon1-ebz/reference_hdl/linux.1611598496.txt.gz · Last modified: 25 Jan 2021 19:14 by Robin Getz