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Simplified Block Diagram | Detailed Block Diagram |
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Measurement | |
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AD7401A | 5 kV rms, isolated 2nd order Sigma-Delta modulator |
ADA4084-2 | 30 V, Low noise, rail-to-rail I/O, low power operational amplifier |
AD8646 | 24 MHz rail-to-rail dual op amp |
AD2S1210 | Variable resolution, 10-bit to 16-bit R/D converter with reference oscillator |
Power | |
ADuM5000 | isoPower® integrated isolated dc-to-dc converter |
ADP1614 | 1000 mA, 2.5 MHz buck-boost dc-to-dc converter |
ADM660 | CMOS switched-capacitor voltage converter |
Isolation | |
ADuM7640 | Triple channel digital isolator |
Voltage Translation | |
ADG3308 | 8-channel bidirectional level translator |
Multiplexers | |
ADG704 | CMOS, low voltage 2.5 Ω 4-channel multiplexer |
ADG759 | CMOS low voltage, 3 ohms 4-channel multiplexer |
High Speed Communication | |
88E1512 | Marvell Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver |
Sensor Selection | ||
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Back EMF | P9 - position 0 | P20 - position 0 |
Single ended Hall | P9 - position 1 | P20 - position 0 |
Differential Hall | P9 - position 0 | P20 - position 1 |
Reserved | P9 - position 1 | P20 - position 1 |
Resolver Comfiguration Mode | ||
Normal Mode - Position input | P3 - Not inserted | P5 - Not inserted |
Normal Mode - Velocity input | P3 - Not inserted | P5 - Inserted |
Reserved | P3 - Inserted | P5 - Not inserted |
Configuration Mode | P3 - Inserted | P5 - Inserted |
Resolver Resolution Settings | ||
10 Bits | P4 - Not inserted | P6 - Not inserted |
12 Bits | P4 - Not inserted | P6 - Inserted |
14 Bits | P4 - Inserted | P6 - Not inserted |
16 Bits | P4 - Inserted | P6 - Inserted |
PHYs Configuration | ||
2.5V VDDO, different PHY addresses | P11 & P12 - Position 0 | P9 - Inserted |
The AD7401 Isolated Sigma-Delta Modulators present on the controller board have a 2 wires signal interface with the FPGA:
The reconstruction of the data provided by the AD7401 modulator can be done using a SINC3 filter. A filter model and HDL implementation are provided in the AD7401 datasheet.
Single digital interface for multiple position sensors
3 digital signals between HW and the FPGA
Sensor selection is done with jumpers on the controller board. The hardware conditions the analog signals and sends clean digital signals to the FPGA.
AD-FMCMOTCON1-EBZ - Schematics + Layout + BOM