The AD-FMCJESDADC1-EBZ is a high speed data acquisition (4 channels at 245.76 MSPS), in a FMC form factor which supports the JESD204B high speed serial interface. This board is one of the few boards that meet all the FMC specifications in terms of mechanical size, and mounting hole locations. For that information, please refer to the FMC specification.
Although this board does meet the FMC specifications, it is not meant as a commercial off the shelf (COTS) board. If you want a commercial, ready to integrate product, please refer to one of the many FMC manufactures, like Abaco.
This board is targeted to use the ADI reference designs, and work with both Altera and Xilinx development systems. ADI provides complete source (HDL and software) to re-create those projects (minus the IP provided by the FPGA vendors, which we use), but may not provide enough info to port this to your custom platform.
The card contains:
The FPGA project can be found on the wiki.
Eye scan or this board can be found at jesd_eye_scan.
The AD-FMCJESDADC1-EBZ board's primary purpose is to easily understand/validate/verify the JESD204B interface with various manufactures FPGA's (We have designs for Altera and Xilinx).
When putting things into the small FMC form factor, various tradeoffs were made which limit the performance to the first nyquist. These tradeoffs in size/power/performance are normally the things that Analog Devices tells its customers not to do to get maximum performance.
The AD-FMCJESDADC1-EBZ uses the AD9517-0. This is a small (7.0mm x 6.75mm), low power (~1.4W) multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. It's driven by a single 30.72 MHz crystal, and generates the necessary clocks for the system (2.45760GHz, 245.760MHz, 30.72MHz).
The ADIsimCLK tool provides the following data about the clocking system on the 245.760MHz (which drive the AD9250) outputs:
Broadband Jitter (>1kHz) = 516fs (rms) SNR = 69.79dB ENOB = 11.63bits at IF Freq = 100 MHz Integrated Phase Noise from 100kHz to 1.25MHz Timing Jitter = 304fs rms Phase Jitter EVM = 0.05% rms Phase Jitter = 0.027 degrees rms ACI/ACR = -69.6dBc Delay from Ref to OUT2 is 420ps
This matches up with the datasheet when using the internal VCO. To improve this number, a external VCXO could have been used (would decrease the jitter to ~54 fs rms), but this would have increased the size, and violated the height requirements of the FMC specification (most VCXO's which good performance are tall).
This is the key aspect of any good converter design - the clock source.
The datasheet for the AD9250 and the golden evaluation board recommend a Differential Double Balun Input Configuration (figure 41 in the datasheet), with this note:
From the AD9250 Datasheet:
At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9250. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 41).
The AD-FMCJESDADC1-EBZ card uses a single differential transformer (Minicircuits TC4-1W) - as shown in figure 40 of the datasheet - due to its smaller size (reduced footprint). The specific transformer used is specified from 3 to 800 MHz, but is only linear (in terms of insertion loss/input return loss) +/- 0.5dB, from 10 to 100MHz (limiting things to the first nyquist, before the converter sees massive losses on the input side.
This transformer was chosen as a good trade off of size (3.8mm x 3.8mm x 3.8mm), Power (250mW of RF), with (Secondary/Primary) impedance (4:1) which operates in the first nyquist.
If you have any questions regarding the AD-FMCJESDADC1-EBZ board or are experiencing any problems while using the board or following the user guides feel free to ask us a question. Questions can be asked on our EngineerZone support community. Calling on the phone, emailing someone directly, will only cause things to get answered in much slower manner.
For questions regarding the AD-FMCJESDADC1-EBZ hardware or the HDL reference design please state them in the FPGA Reference Designs sub-community. If you have questions about the tools, please go ask the tools vendors:
For questions regarding the the ADI Linux distribution, the Linux drivers, or the device trees for the AD9250 based platforms, please use the Linux Software Drivers sub-community.
If you have generic userspace questions (how do I use a standard linux tool), we should suggest to use your favorite search tool to find that tool/utility/application support method (some use email, some use web). If you think you have found a bug specific to ARM, please report this upstream.
For questions regarding the no-OS drivers for AD9250, please use the Microcontroller and No-OS Driver sub-community.
Questions about the AD9250, please use the AD9250 sub-community.