The reference design is a processor based (ARM, Nios II or Microblaze) embedded system. A functional block diagram of the system is given below. The devices interfaces are shared by the same set of transceivers followed by the individual JESD204B and ADC/DAC pcores. The cores are programmable through an AXI-lite interface. The data path consists of independent DMA interfaces for the transmit and receive paths.
The digital interface consists of 4 transmit and 4 receive lanes running at 12.33Gbps (default). The transceivers then interface to the cores at firstname.lastname@example.orgMHz. The data is sent or received based on the configuration (programmable) from separate transmit and receive chains.
The DAC data may be sourced from an internal data generator (DDS, pattern or PRBS) or from the external DDR via DMA. The internal DDS phase and frequency are programmable.
The ADC data is sent to the DDR via DMA. The core also supports PN monitoring at the sample level. This is different from the JESD204B specific PN sequence (though they both claim to be from the same equation).
The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.
These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done.
Our recommended platforms are the Zynq based systems:
but it also works on the following fabric only systems:
We are in the process of adding Zynq Ultrascale support:
For Altera systems: