NO-OS Project Build Guide
NOTE: This build guide is valid for the projects found in the
no-OS/projects folder. If your project resides elsewhere under the no-
OS repository tree, it is a legacy project. A build guide for legacy projects can be found
Build no-OS with GNU make.
Clone NO-OS with the --recursive
flag:
git clone --recursive https://github.com/analogdevicesinc/no-OS
If however you've already cloned NO-OS without the --recursive
flag, you may initialize all the submodules in an existing NO-OS clone with:
git submodule update --recursive --init
Build Prerequisites
Prior to building a no-OS project, it is required to set up some environment variables so that the build process may find the necessary tools (compiler, linker, SDK etc.).
Use the following commands to prepare your environment for building no-OS projects:
Assuming the SDK is installed at this path:
/path/to/intel
└── intelFPGA
└── 18.1
Run:
$ source no-OS/tools/scripts/platform/intel/environment.sh /path/to/intel/intelFPGA 18.1
Assuming the Vitis is installed at this path:
/path/to/xilinx
├── DocNav
├── Downloads
├── SDK
│ └── 2019.1
└── Vitis
└── 2021.1
When using no-OS master branch, run:
$ source /path/to/xilinx/Vitis/2021.1/settings64.sh
When using no-OS 2019_R2 branch, run:
$ source /path/to/xilinx/SDK/2019.1/settings64.sh
For more information, consult the support/answers/47821.html.
-
Set the MAXIM_LIBRARIES environment variable to the MaximSDK/Libraries path (the default should be ~/MaximSDK/Libraries).
For visual debugging and building, install Visual Studio Code
, and the Cortex-Debug
extension.
-
Set the PICO_SDK_PATH environment variable to the pico-sdk cloned repository path.
-
Set the JLINK_SERVER_PATH environment variable to the JLinkGDBServerCLExe path (the default path should be /opt/SEGGER/JLink/JLinkGDBServerCLExe).
For visual debugging and building, install Visual Studio Code
, and the Cortex-Debug
extension.
ADuCM3029 (Click to expand)
ADuCM3029 (Click to expand)
Please install all the necessary packs locally and then manually import them in CrossCore
Common Issues with environment setup:
Windows (Click to expand)
Windows (Click to expand)
Use cmd or PowerShell. Cygwin is not supported.
Assuming the SDK is installed at this path:
C:\
└── intelFPGA
└── 18.1
Run:
> .\no-OS\tools\scripts\platform\altera\environment.bat C:\intelFpga 18.1
Assuming the Vitis is installed at this path:
C:\Xilinx
├── DocNav
├── Downloads
├── SDK
│ └── 2019.1
└── Vitis
└── 2021.1
When using no-OS master branch, run:
> C:\Xilinx\Vitis\2021.1\settings64.bat
When using no-OS 2019_R2 branch, run:
> C:\Xilinx\SDK\2019.1\settings64.bat
For more information, consult the Xilinx support support/answers/47821.html.
Note that Xilinx SDK versions 2018.3 or earlier don't properly set up the Windows PATH so that you may use make command provided with the SDK from the shell.
If this is the case, please manually add the following to your Windows PATH or install make for Windows of your choice:
C:\Xilinx\SDK\2018.3\gnuwin\bin
-
Set the MAXIM_LIBRARIES environment variable to the MaximSDK\Libraries path (the default should be C:\MaximSDK\Libraries).
For visual debugging and building, install Visual Studio Code
, and the Cortex-Debug
extension.
ADuCM3029 (Click to expand)
ADuCM3029 (Click to expand)
Please install all the necessary packs locally and then manually import them in CrossCore
Common Issues with environment setup:
If using PowerShell instead of cmd, open another shell instance after running the above scripts.
Building a project
Go in the project directory that should be built.
$ cd no-OS/projects/project_name/
$ tree
.
├── builds.json
├── Makefile
├── src
└── src.mk
Copy the .sof and .sopcinfo to the project folder.
$ ls
Makefile profiles src src.mk system_bd.sopcinfo adrv9009_a10gx.sof
$ make
# Alternatively you may select a .sopcinfo file explicitly by:
$ make HARDWARE=path/to/system_bd.sopcinfo
Copy the .hdf in the project folder.
$ ls
Makefile profiles src src.mk system_top.hdf
$ make
# Alternatively you may select an .hdf file explicitly by:
$ make HARDWARE=path/to/file.hdf
To build a project, type:
make PLATFORM=maxim TARGET=...
The TARGET
specifies the chip for which the project is built. If it is missing, max32660
will be used. At the moment, the available targets are: max32650
, max32655
and max32660
.
To build a project, type:
make PLATFORM=pico
Make sure you have the .ioc file in the project directory, then type:
$ make
ADuCM3029 (Click to expand)
ADuCM3029 (Click to expand)
The ADuCM3029 projects also contain a pinmux_config.c
file which contains pin configuration instructions.
# build an ADuCM3029-only project
$ make
# if the platform autodetection picks the wrong platform, explicitly specify the PLATFORM
$ make PLATFORM=aducm3029
Windows (Click to expand)
Windows (Click to expand)
CMD needs to be run with
administrative privileges to create a project.
If this is not possible, check the standalone section.
> cd .\no-OS\projects\project_name\
It should contain make-related files and source files:
.\no-OS\projects\project_name\
├── builds.json
├── Makefile
├── src
└── src.mk
Copy the .sof and .sopcinfo to the project folder and run:
.\no-OS\projects\adrv9009\
├── Makefile
├── profiles
├── src
├── src.mk
├── system_bd.sopcinfo
└── adrv9009_a10gx.sof
> make
Copy the .hdf to the project folder and run:
.\no-OS\projects\adrv9009\
├── Makefile
├── profiles
├── src
├── src.mk
└── system_top.hdf
> make
To build a project, type:
make PLATFORM=maxim TARGET=...
The TARGET
specifies the chip for which the project is built. If it is missing, max32660
will be used. At the moment, the available targets are: max32650
, max32655
and max32660
.
ADuCM3029 (Click to expand)
ADuCM3029 (Click to expand)
The ADuCM3029 projects also contain a pinmux_config.c
file which contains pin configuration instructions.
# build an ADuCM3029-only project
> make
# if the platform autodetection picks the wrong platform, explicitly specify the PLATFORM
> make PLATFORM=aducm3029
The build process creates a build directory in the project folder:
build
├── app
├── bsp
├── obj
├── release.elf
└── tmp
Running/Debugging
Once the .elf
or .hex
file has been generated, make sure the board is powered on, JTAG cable connected and use the following commands to upload the program to the board or debug.
Uploading the binary to target is generically achieved with:
$ make run
Use the following command to launch the SDK associated to the used platform in order to be able to debug graphically by clicking the debug button:
$ make sdkopen
Fore more details about the available make rules, check out this page.
Build no-OS with GNU make
This guide provides some quick instructions on how to build and run the no-OS on almost all of the supported platforms.
Be sure you are using the latest release version and you have the corresponding branches for both HDL and no-OS(Release notes).
Building the HDL
ADI does not distribute the bit/elf files of these projects. They must be built from the sources. The HDL User Guide provides detailed information and steps to build the HDL project on your desired carrier. The build flow is developed around GNU make. You may use a Windows or Linux OS, but do NOT seek OS- specific support. The prerequisite to the building process is that you are able to run 'quartus', 'vivado' and 'make' all from a shell (Cygwin or Linux).
Building the HDL is as simple as running make on your desired project and carrier.
hdl/projects/daq3/kcu105> make
hdl/projects/daq3/zc706> make
For Intel nios2 based processor projects you have to turn off the MMU (Memory Management Unit used for Linux
OS) when building the HDL.
hdl/projects/daq3/a10gx> make MMU=0
We strongly recommend having a clone of no-Os and HDL in the same folder:
~/github/hdl/
~/github/no-OS/
In every project folder, you can find a separate subfolder for each supported carrier. In each carrier folder, there is a Makefile which points to the bit files and HDL deliverables (system_top.hdf/project_name.sof) and other makefiles (*.mk) containing the software dependencies.
Building the software
Change your current directory to your targeted project and run make:
[~] cd fmcdaq2/zc706
[~] make
See Troubleshooting section for guideline how to solve make related issues.
Running the software
Make sure that the FPGA is powered on and connected to the PC and then run the command:
[~] make run
The make run will downloads the bitstream on the FPGA and after that program the board with the elf file.
The software is started before the memory debugger disconnects.
Evaluating the result
After the software has been run on the FPGA, run the command:
[~] make capture
By default, the software captures (in case of ADC based projects) the data received from the device in the RAM.
rx_xfer.start_address = *_MEM_BASEADDR + OFFSET;
rx_xfer.no_of_samples = value;
dmac_start_transaction(ad_core_dma);
These values differ depending on the architecture and device.
The Makefiles have these parameters initialized with default values:
The number of samples is specified in the project's common Makefile. (ex: fmcadc4)
The script will write a capture_chx.csv file for every channel.
In the case of an RF device which has I and Q data for each channel, the number of capture_chx.csv files will double.
For example, for fmcomms2(AD9361: 2RF channels):
fmcomms2 |
channel1 | data I | capture_ch1.csv |
| data Q | capture_ch2.csv |
channel2 | data I | capture_ch3.csv |
| data Q | capture_ch4.csv |
Clean the workspace
Troubleshooting
make: *** No rule to make target `../../../hdl/projects/daq2/vc707/daq2_vc707.sdk/system_top.hdf', needed by `hw/system_top.bit'. Stop.
The HDL deliverables cannot be found. Maybe the targeted HDL project is not built, or the defined path is not valid. Make sure, that you build the HDL before running the no-OS or specify the location of the HDL deliverables explicitly.
For Xilinx
[~] make HARDWARE=/<path_to_hdf>/system_top.hdf
For Intel
[~] make M_SOPCINFO_FILE=/<path_to_sopcinfo>/system_bd.sopcinfo
Understanding/Modifying things
The best place to start in the no-OS main function in “project/project_name.c”. It shows how individual components of a data path chain are initialized and programmed for the application. After you have the default setup working, feel free to add your own customization routines and/or signal processing functions to either HDL or no-OS.
Some applications (
e.g. FMCOMMSx), when a Microblaze processor is used, requires an increased HEAP size for dynamic memory allocation. Make sure the HEAP size is at least
0x100000.
//#define XILINX
#define ALTERA
After the FPGA was programmed, we need to create a new Run configuration, by selecting Run → Run Configurations…, in the Run Configuration windows select the Xilinx C/C++ application (System Debugger) and click at the New Configuration button at the upper left corner.
If your target carrier has a Zync SoC, make sure, that you specify the Initialization file, and select the Run ps7_init and Run ps7_post_config options.
The output of the example program can be viewed in the SDK console by enabling the Connect STDIO Console option and setting the baud rate of the
UART port to 115200.
As an alternative a
UART terminal can be used to capture the output of the example program. The number of used
UART port depends on the computer's configuration. The following settings must be used in the
UART terminal:
Baud Rate: 115200bps
Data: 8 bit
Parity: None
Stop bits: 1 bit
Flow Control: none