This version (14 Dec 2020 15:23) was approved by Stanca-Florina Pop.The Previously approved version (20 Nov 2019 12:42) is available.
Table of Contents
AD-FMCDAQ2-EBZ HDL Reference Design
Functional Overview
The reference design is a processor based (ARM or Microblaze/Nios2) embedded system. A functional block diagram of the system is given below for both Xilinx and Altera FPGAs. The device interfaces are shared by the same set of transceivers followed by the individual JESD204B and ADC/DAC pcores. The cores are programmable through an AXI-lite interface. The data path consists of independent DMA interfaces for the transmit and receive paths.
AD-FMCDAQ2-EBZ block diagram
Xilinx block diagram
Altera block diagram
Digital Interface
The digital interface consists of 4 transmit and 4 receive lanes running at 10Gbps (default). The transceivers then interfaces to the cores at 128bits@250MHz. The data is sent or received based on the configuration (programmable) from separate transmit and receive chains.
Altera specific
When using Qsys, implementing JESD204B protocol requires several IPs. AVL_XCVR is a wrapper which instantiates all the required IPs and configures them according to the desired data rate. One AVL_XCVR must be instantiated for the transmit path and one for the receive path. It adds clock bridges, PLL and reconfiguration IP, proper reset, lane PLL for the transmit path, a JESD204B IP instantiating the JESD204B base and a JESD204B IP for each lane instantiating the PHY.
AXI_XCVR allows resetting and monitoring the transceiver path.
One important aspect for AD-FMCDAQ2-EBZ is that the reference clock needed for the FPGA transceiver calibration is generated only after the AD9523-1 clock generator is configured. The programming is done only after the FPGA is configured and software is running. Because of this, the software needs to perform a transceiver re-calibration after the transceiver reference clock is stable and before taking AXI_XCVR cores out of reset.
DAC Interface
The DAC data may be sourced from an internal data generator (DDS, pattern or PRBS) or from the external DDR via DMA. The internal DDS phase and frequency are programmable.
ADC Interface
The ADC data is sent to the DDR via DMA. The core also supports PN monitoring at the sample level. This is different from the JESD204B specific PN sequence (though they both claim to be from the same equation).
Control and SPI
The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.
Supported Carriers
These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done.
Our recommended plaforms are the Zynq based systems:
but it also works on the following fabric only systems:
For Altera systems:
Download
FMCDAQ2
| Hardware | Project | Carriers | Resource Utilization | Library Cores |
|---|---|---|---|---|
| AD-FMCDAQ2-EBZ | daq2 | a10soc | NA | ad_ip_jesd204_tpl_adc |
| kc705 | daq2_kc705 | ad_ip_jesd204_tpl_dac | ||
| kcu105 | daq2_kcu105 | axi_adxcvr | ||
| zc706 | daq2_zc706 | axi_clkgen | ||
| zcu102 | daq2_zcu102 | axi_dmac | ||
| axi_hdmi_tx | ||||
| axi_jesd204_rx | ||||
| axi_jesd204_tx | ||||
| axi_spdif_tx | ||||
| axi_sysid | ||||
| data_offload | ||||
| jesd204_rx | ||||
| jesd204_tx | ||||
| sysid_rom | ||||
| util_adcfifo | ||||
| util_adxcvr | ||||
| util_axis_fifo | ||||
| util_cdc | ||||
| util_cpack2 | ||||
| util_do_ram | ||||
| util_hbm |
Help & Support
- The carriers (abbrevations can be found here) are commonly available FPGA evaluation boards.
- The HDL user guide contains all the documentation, build instructions and register map tables.
- The following quick links allows you to browse the github repository for a list of current branches, library components, and projects.
resources/eval/user-guides/ad-fmcdaq2-ebz/reference_hdl.txt · Last modified: 14 Dec 2020 15:23 by Stanca-Florina Pop