The [[http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcdaq2-ebz.html#eb-overview|AD-FMCDAQ2-EBZ]] module is comprised of the [[http://www.analog.com/en/products/analog-to-digital-converters/high-speed-ad-10msps/high-if-ad-converters/ad9680.html|AD9680]] dual, 14-bit, 1.0 GSPS, JESD204B ADC, the [[http://www.analog.com/en/products/digital-to-analog-converters/da-converters/ad9144.html|AD9144]] quad, 16-bit, 2.8 GSPS, JESD204B DAC, the [[http://www.analog.com/en/products/clock-and-timing/clock-generation-distribution/ad9523-1.html#product-overview|AD9523-1]] clock, and power management components. It is clocked by an internally generated carrier platform via the FMC connector, comprising a completely self contained data acquisition and signal synthesis prototyping platform. In an FMC footprint (84 mm × 69 mm), the module’s combination of wideband data conversion, clocking, and power closely approximates real-world hardware and software for system prototyping and design, with no compromise in signal chain performance. | The [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcdaq2-ebz.html#eb-overview|AD-FMCDAQ2-EBZ]] module is comprised of the [[adi>en/products/analog-to-digital-converters/high-speed-ad-10msps/high-if-ad-converters/ad9680.html|AD9680]] dual, 14-bit, 1.0 GSPS, JESD204B ADC, the [[adi>en/products/digital-to-analog-converters/da-converters/ad9144.html|AD9144]] quad, 16-bit, 2.8 GSPS, JESD204B DAC, the [[adi>en/products/clock-and-timing/clock-generation-distribution/ad9523-1.html#product-overview|AD9523-1]] clock, and power management components. It is clocked by an internally generated carrier platform via the FMC connector, comprising a completely self contained data acquisition and signal synthesis prototyping platform. In an FMC footprint (84 mm × 69 mm), the module’s combination of wideband data conversion, clocking, and power closely approximates real-world hardware and software for system prototyping and design, with no compromise in signal chain performance. |