The most recent version of this page is a draft.
This version is outdated by a newer approved version.This version (04 Nov 2016 12:49) was approved by Lucian Sin.The Previously approved version (05 Apr 2016 11:17) is available.
This version is outdated by a newer approved version.This version (04 Nov 2016 12:49) was approved by Lucian Sin.The Previously approved version (05 Apr 2016 11:17) is available.This is an old revision of the document!
Table of Contents
AD-FMCDAQ2-EBZ Functional Overview
A functional block diagram of the system is given below. The system consists of four functional partitions - transmit path, receive path, clocking and power supply.
Transmit
Key component:
| AD9144 | Quad, 16-Bit, 2800 MSPS, TxDAC+® Digital-to-Analog JESD204B Converter with offset, phase and gain compensation. |
The reference design generates the signals for AD9144 either from an internal DDS or external memory (via VDMA). The internal DDS consists of four independent signal generators with programmable phase offset and frequency. These four signal generators are paired to create two tones that are interleaved and driven to the DAC.
Receive
Key component:
| AD9680 | 14-Bit, 1000 MSPS, Dual Analog-to-Digital JESD204B Converter (ADC). |
The reference design transfers the received data to DDR via DMA. An optional off-line FFT core may be used to generate a spectrum plot.
Clocking
Key component:
| AD9523-1 | Low Jitter Clock Generator (1MHz to 1GHz) with 14 Outputs. |
The system is clocked through an on board crystal (125MHz). The clock path mainly consists the AD9523-1 which upconverts this signal to ~3GHz, and then divides this back down to any integer dividor of this ~3GHz output.
The default reference design that ADI provides does the following:
- Crystal generates a fixed clock frequency of 125MHz.
- This clock is sent to the AD9523-1.
- The AD9523 takes this, and creates:
- 1000 MHz for the DAC sample rate
- 1000 MHz for the ADC sample rate
- 500 MHz for the reference clocks to FPGA
These clocks can be changed, but the key thing to remember is that the AD9523-1 drives both the ADC and DAC. The AD9523-1 has two clock banks (see figure 1 in the datasheet), Bank 0: 0-3 & 10-13, and Bank 1: 4-9. The outputs on the different banks need to be integer mutliples of eachother. The best thing to do if you are interested in the details of this, is to get the Eval board software, and play with the different settings (you don't need a demo board connected to run the software).
Power
Key components:
| ADP2384 | 4A, 20V step-down switcher. |
| ADP7104 | High accuracy, 500mA LDO |
| ADP150 | Ultra low noise, 150/200 mA LDO |
| ADP1740 | Low VIN, 2A LDO |
| ADP1741 | Low VIN, 2A LDO |
| ADP1755 | Low VIN, 1.2A LDO |
The board receives all the power from the FPGA board through FMC.
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resources/eval/user-guides/ad-fmcdaq2-ebz/hardware/functional_overview.1478260061.txt.gz · Last modified: 04 Nov 2016 12:47 by Lucian Sin