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resources:eval:user-guides:ad-fmcdaq2-ebz:clocking [12 Sep 2017 18:13] – [Overview] Lars-Peter Clausen | resources:eval:user-guides:ad-fmcdaq2-ebz:clocking [19 Jan 2018 10:14] (current) – rename xcomm_zynq -> master Alexandru Ardelean | ||
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- | Rearranging these formulas it is possible to compute the A and B counter settings from a know reference and a desired VCO frequency. | + | Rearranging these formulas it is possible to compute the A and B counter settings from a known reference and a desired VCO frequency. |
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On Linux the default clock configuration is supplied through the [[https:// | On Linux the default clock configuration is supplied through the [[https:// | ||
- | The devicetree file that is used for the AD-FMCDAQ2-EBZ and contains the clock configuration is called [[linux.github> | + | The devicetree file that is used for the AD-FMCDAQ2-EBZ and contains the clock configuration is called [[linux.github> |
To change the clocking configuration the properties of the AD9523-1 node can be modified. The following lists the most important properties for the AD-FMCDAQ2-EBZ and their corresponding hardware setting. The function of each of these settings and how to choose their value has been discussed above. For more information refer to the [[: | To change the clocking configuration the properties of the AD9523-1 node can be modified. The following lists the most important properties for the AD-FMCDAQ2-EBZ and their corresponding hardware setting. The function of each of these settings and how to choose their value has been discussed above. For more information refer to the [[: | ||
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| Frequency of the external VCXO | '' | | Frequency of the external VCXO | '' | ||
| PLL2 reference divider (R2) | '' | | PLL2 reference divider (R2) | '' | ||
- | | PLL2 feedback | + | | PLL2 feedback divider |
- | | PLL2 feedback | + | | PLL2 feedback divider |
| PLL2 VCO output divider (M1) | '' | | PLL2 VCO output divider (M1) | '' | ||