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| resources:eval:user-guides:ad-fmcdaq2-ebz:clocking [12 Sep 2017 18:00] – [No-OS] Lars-Peter Clausen | resources:eval:user-guides:ad-fmcdaq2-ebz:clocking [19 Jan 2018 10:14] (current) – rename xcomm_zynq -> master Alexandru Ardelean | ||
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| The ADC and DAC converter clocks are the reference clock for the ADC and DAC respectively and determine the sampling rate of the converter. If a deterministic latency relationship between the DAC and ADC datapath is required the DAC and ADC clock need to be in a (sub-)harmonic relationship to each other, otherwise their relationship can be chosen freely. | The ADC and DAC converter clocks are the reference clock for the ADC and DAC respectively and determine the sampling rate of the converter. If a deterministic latency relationship between the DAC and ADC datapath is required the DAC and ADC clock need to be in a (sub-)harmonic relationship to each other, otherwise their relationship can be chosen freely. | ||
| - | The ADC FPGA reference clock is the reference clock for the JESD204 clock-data-recovery (CDR) circuit as well the ADC data path inside the FPGA. Similarly | + | The DAC has built-in interpolation filters that allow interpolation by a factor of 2, 4 or 8. The interpolation factor and the DAC converter sample-rate decide |
| - | The SYSREF clocks are used for synchronization and to establish deterministic latency between the different components. The SYSREF clock must be a integer multiple of the local-multi-frame-clock (LMFC). The LMFC is a clock that is generated internally in the converters and FPGA and on the AD-FMCDAQ2-EBZ platform it's rate is 1/32 of the converter | + | The ADC has built-in decimation filters that allow interpolation by a factor of 2, 4, 8 or 16. The decimation factor and the ADC converter sample-rate decide the ADC data-output-rate. The data-output-rate is equal to the sample-rate divided by the decimation factor. |
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| + | The JESD204 lane rates depend on the data-output/ | ||
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| + | The ADC FPGA reference clock is the reference clock for the JESD204 clock-data-recovery (CDR) circuit as well the ADC data path inside the FPGA. Similarly the DAC FPGA reference clock is the reference clock for the JESD204 transmit PLL and the DAC data path inside the FPGA. These clocks should be set to the JESD204 lane-rate divided by 20. | ||
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| + | The SYSREF clocks are used for synchronization and to establish deterministic latency between the different components. The SYSREF clock must be a integer multiple of the local-multi-frame-clock (LMFC). The LMFC is a clock that is generated internally in the converters and FPGA and on the AD-FMCDAQ2-EBZ platform it's rate is 1/32 of the converter | ||
| The SYSREF clocks going to the converter and the FPGA must be configured for the same frequency. If a deterministic latency relationship between the DAC and ADC datapath is required the DAC and ADC SYSREF signals must be configured for the same frequency, otherwise the DAC and ADC datapath SYSREF clocks can be configured with different frequencies. | The SYSREF clocks going to the converter and the FPGA must be configured for the same frequency. If a deterministic latency relationship between the DAC and ADC datapath is required the DAC and ADC SYSREF signals must be configured for the same frequency, otherwise the DAC and ADC datapath SYSREF clocks can be configured with different frequencies. | ||
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| | DAC converter clock | ≥ 200 MHz, ≤ 1000 MHz, Master clock / N< | | DAC converter clock | ≥ 200 MHz, ≤ 1000 MHz, Master clock / N< | ||
| | DAC SYSREF clock | DAC converter clock / (N< | | DAC SYSREF clock | DAC converter clock / (N< | ||
| - | | ADC JESD204 lane rate | ADC converter clock / ADC decimation factor * 1000 | | + | | ADC JESD204 lane rate | ADC converter clock / ADC decimation factor * 10 | |
| - | | DAC JESD204 lane rate | DAC converter clock / DAC interpolation factor * 1000 | | + | | DAC JESD204 lane rate | DAC converter clock / DAC interpolation factor * 10 | |
| ===== Examples ===== | ===== Examples ===== | ||
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| '' | '' | ||
| - | Rearranging these formulas it is possible to compute the A and B counter settings from a know reference and a desired VCO frequency. | + | Rearranging these formulas it is possible to compute the A and B counter settings from a known reference and a desired VCO frequency. |
| '' | '' | ||
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| On Linux the default clock configuration is supplied through the [[https:// | On Linux the default clock configuration is supplied through the [[https:// | ||
| - | The devicetree file that is used for the AD-FMCDAQ2-EBZ and contains the clock configuration is called [[linux.github> | + | The devicetree file that is used for the AD-FMCDAQ2-EBZ and contains the clock configuration is called [[linux.github> |
| To change the clocking configuration the properties of the AD9523-1 node can be modified. The following lists the most important properties for the AD-FMCDAQ2-EBZ and their corresponding hardware setting. The function of each of these settings and how to choose their value has been discussed above. For more information refer to the [[: | To change the clocking configuration the properties of the AD9523-1 node can be modified. The following lists the most important properties for the AD-FMCDAQ2-EBZ and their corresponding hardware setting. The function of each of these settings and how to choose their value has been discussed above. For more information refer to the [[: | ||
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| | Frequency of the external VCXO | '' | | Frequency of the external VCXO | '' | ||
| | PLL2 reference divider (R2) | '' | | PLL2 reference divider (R2) | '' | ||
| - | | PLL2 feedback | + | | PLL2 feedback divider |
| - | | PLL2 feedback | + | | PLL2 feedback divider |
| | PLL2 VCO output divider (M1) | '' | | PLL2 VCO output divider (M1) | '' | ||
resources/eval/user-guides/ad-fmcdaq2-ebz/clocking.1505232026.txt.gz · Last modified: 12 Sep 2017 18:00 by Lars-Peter Clausen