This version is outdated by a newer approved version.
This version (01 Sep 2017 09:29) was approved by Lars-Peter Clausen.
This version (01 Sep 2017 09:29) was approved by Lars-Peter Clausen.This is an old revision of the document!
Table of Contents
AD-FMCDAQ2-EBZ Clocking
The AD9523-1 is responsible for generating and distributing all clock signals used on the AD-FMCDAQ2-EBZ platform.
The AD-FMCDAQ2-EBZ platform only uses the second PLL of the AD9523-1 with the reference for the PLL being sourced from a external 125 MHz crystal. The PLL2 VCO has a locking range of 2910 MHz to 3100 MHz, with the external reference being 125 MHz the nominal output frequency of the VCO is 3000 MHz.
The output of the PLL VCO is down divided to the target frequencies in two steps. First it is divided by either 3, 4 or 5, which gives a frequency of 1000 MHz, 750 MHz or 600 MHz respectively. This is the master clock frequency for the data converter system and shared between the DAC and ADC data path, all generated clocks are based of this master clock.
The master clock is distributed to each clock output and further down divided by an integer divider in the range of 1-1024. On the AD-FMCDAQ2-EBZ platform 8 different clocks are generated this way, 4 each for the DAC and ADC datapath.
| Clock Output | Function |
|---|---|
| OUT1 | DAC converter clock |
| OUT4 | ADC FPGA reference clock |
| OUT5 | ADC converter SYSREF clock |
| OUT6 | ADC FPGA SYSREF clock |
| OUT7 | DAC FPGA SYSREF clock |
| OUT8 | DAC converter SYSREF clock |
| OUT9 | DAC FPGA reference clock |
| OUT13 | ADC converter clock |
| Other | Unused |
The ADC and DAC converter clocks are the reference clock for the ADC and DAC respectively and determine the sampling rate of the converter. If a deterministic latency relationship between the DAC and ADC datapath is required the DAC and ADC clock need to be in a (sub-)harmonic relationship to each other, otherwise their relationship can be chosen freely.
The ADC FPGA reference clock is the reference clock for the JESD204 clock-data-recovery (CDR) circuit as well the ADC data path inside the FPGA. Similarly the DAC FPGA reference clock is the reference clock for the JESD204 transmit PLL and the DAC data path inside the FPGA.
The SYSREF clocks are used for synchronization and to establish deterministic latency between the different components. The SYSREF clock must be a integer multiple of the local-multi-frame-clock (LMFC). The LMFC is a clock that is generated internally in the converters and FPGA and on the AD-FMCDAQ2-EBZ platform it's rate is 1/32 of the converter samplerate. This means the SYSREF clock frequency must be integer down divided of the converter samplerate / 32 (I.e. samplerate / {32, 64, 96, 128, …}).
The SYSREF clocks going to the converter and the FPGA must be configured for the same frequency. If a deterministic latency relationship between the DAC and ADC datapath is required the DAC and ADC SYSREF signals must be configured for the same frequency, otherwise the DAC and ADC datapath SYSREF clocks can be configured with different frequencies.
| Clock | Frequency range | Comments |
|---|---|---|
| PLL2 VCO | 3000 MHz | Tuning range of 2910 MHz to 3100 MHz |
| Master clock | 1000 MHz, 750 MHz, 600 MHz | PLL2 VCO divided by 3, 4 or 5 |
| ADC converter clock | ≥ 312.5 MHz, ≤ 1000 MHz, Master clock / NADC | |
| ADC SYSREF clock | ADC converter clock / (NADC_SYSREF * 32) | |
| DAC converter clock | ≥ 200 MHz, ≤ 1000 MHz, Master clock / NDAC | |
| DAC SYSREF clock | DAC converter clock / (NDAC_SYSREF * 32) | |
| ADC JESD204 lane rate | ADC converter clock * 1000 | |
| DAC JESD204 lane rate | DAC converter clock * 1000 |
Examples
fDAC = 1000 MSPS, fADC = 1000 MSPS
This is the default AD-FMCDAQ2-EBZ configuration with both converters running at the maximum supported samplerate of 1 GSPS.
| Clock | Frequency | Divider setting |
|---|---|---|
| Master clock | 1000 MHz | 3 |
| ADC converter clock | 1000 MHZ | 1 |
| ADC FPGA reference clock | 500 MHZ | 2 |
| ADC SYSREF clock | 7.8125 MHZ | 128 |
| ADC FPGA SYSREF clock | 7.8125 MHZ | 128 |
| ADC JESD204 lane rate | 10 Gbps | |
| DAC converter clock | 1000 MHZ | 1 |
| DAC FPGA reference clock | 500 MHZ | 2 |
| DAC SYSREF clock | 7.8125 MHZ | 128 |
| DAC FPGA SYSREF clock | 7.8125 MHZ | 128 |
| DAC JESD204 lane rate | 10 Gbps |
fDAC = 250 MSPS, fADC = 375 MSPS
Non-harmonic DAC and ADC sampling rate (No deterministic latency between DAC and ADC datapath).
| Clock | Frequency | Divider setting |
|---|---|---|
| Master clock | 750 MHz | 4 |
| ADC converter clock | 375 MHZ | 2 |
| ADC FPGA reference clock | 187.5 MHZ | 4 |
| ADC SYSREF clock | 2.9296875 MHZ | 256 |
| ADC FPGA SYSREF clock | 2.9296875 MHZ | 256 |
| ADC JESD204 lane rate | 3.75 Gbps | |
| DAC converter clock | 250 MHZ | 3 |
| DAC FPGA reference clock | 125 MHZ | 6 |
| DAC SYSREF clock | 1.953125 MHZ | 384 |
| DAC FPGA SYSREF clock | 1.953125 MHZ | 384 |
| DAC JESD204 lane rate | 2.5 Gbps |
resources/eval/user-guides/ad-fmcdaq2-ebz/clocking.1503553474.txt.gz · Last modified: 24 Aug 2017 07:44 by Lars-Peter Clausen