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AD-FMCADC7-EBZ FMC Board

Introduction

ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards.

Hardware

The AD-FMCADC-EBZ board's primary purpose is to demonstrate the capabilities of the devices on board quickly and easily by providing a seamless interface to an FMC carrier platform and running the reference design on the carrier FPGA. The board is designed to self power and self clock when connected to the FMC carrier. The analog signals ( AIN+ and AIN-) are connected to J202 and J201. This rapid prototyping board is default set up with a dc coupled input path.

Devices

The FMC board includes the following products by Analog Devices:

  • AD9680 14-bit dual channel ADC with sampling speeds of up to 1250 MSPS, with a JESD204B digital interface.
  • ADA4961 Low Distortion, 3.2 GHz, RF Digital Gain Amplifier.
  • AD9528 JESD204B Clock Generator with 14 LVDS Outputs
  • ADP2384 20 V, 4 A, Synchronous, Step-Down DC-to-DC Regulator
  • ADP7104 is a 20V, 500mA, low noise, CMOS LDO
  • ADM7154 600 mA, Ultra Low Noise, High PSRR, RF Linear Regulator
  • ADM7172 6.5 V, 2 A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO
  • ADP1741 is a 2A, low Vin, low dropout, CMOS linear regulator

                                                 Top View

                                                 Bottom View

Clocking

The AD-FMCADC4-EBZ includes an on-board 80MHz reference oscillator from Crystek. This feature can be disconnected and an external reference can be applied through J901. When referencing the schematic make sure the proper component changes are made in order to directly route the input into the AD9528.

Analog Front End

The AD-FMCADC4-EBZ uses a passive front end designed for very wide bandwidth. A single ended input needs to be provided to the analog inputs mentioned earlier. A 1:2 impedance ratio broadband balun then converts the input signal differentially to the ADA4961 inputs and has a 1.6GHz bandwidth at -3dB. Each channel amplifier can be adjusted independently in terms of gain.

Revision A

The revision A board supports amplifier gain control via spi. After power-up, the gain of the amplifier defaults to an attenuated state. Use a low jitter, low noise signal source with a level at -20dBm to the analog inputs (J301-A/B/C/D). Apply a signal source no greater than -10dBm to achieve full-scale of the converter when maximum gain of the amplifier is applied.

Downloads (Hardware)

Downloads (HDL)

Projects list and dependencies for master

AD40XXFMC

AD469XFMC

AD5758SDZ

AD5766SDZ

AD6676EVB

AD7134FMC

AD738xFMC

AD7405FMC

AD7616SDZ

AD77681EVB

AD7768EVB

AD9081FMCAEBZ

AD9082FMCAEBZ

AD9083EVB

AD9208DUALEBZ

AD9265FMC

AD9434FMC

AD9467FMC

AD9656FMC

AD9739AFMC

ADFMCLIDAR1EBZ

ADAQ7980SDZ

ADRV9001

ADRV9008/9

ADRV9371

ADV7511OnBoard

ADV7513OnBoard

Hardware Project Carriers Resource Utilization Library Cores
ADV7513 adv7513 de10nano NA axi_dmac
axi_hdmi_tx
util_axis_fifo

ARRadio

Hardware Project Carriers Resource Utilization Library Cores
ARRadio arradio c5soc NA axi_ad9361
axi_dmac
axi_sysid
sysid_rom
util_axis_fifo
util_cdc
util_cpack2
util_rfifo
util_upack2

CN0363

CN0501

Hardware Project Carriers Resource Utilization Library Cores
CN0501 cn0501 coraz7s cn0501_coraz7s axi_dmac
axi_generic_adc
axi_sysid
sysid_rom
util_axis_fifo
util_cdc

CN0506MII

CN0506RGMII

CN0506RMII

Hardware Project Carriers Resource Utilization Library Cores
CN0506 cn0506_rmii zc706 NA axi_clkgen
zcu102 NA axi_dmac
zed NA axi_hdmi_tx
axi_i2s_adi
axi_spdif_tx
axi_sysid
sysid_rom
util_axis_fifo
util_cdc

CN0540

DACFMCEBZ

FMCDAQ2

FMCDAQ3

FMCADC2/FMCADC3

FMCADC5

FMCJESDADC1

FMCOMMS11

FMCOMMS2/FMCOMMS3/FMCOMMS4

FMCOMMS5

FMCOMMS8

FMCIMAGEONG

Help & Support

Help & Support

Downloads (Linux)

resources/eval/user-guides/ad-fmcadc7-ebz.1447767004.txt.gz · Last modified: 17 Nov 2015 14:30 by michael gibson