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resources:eval:user-guides:ad-fmcadc7-ebz [16 Nov 2015 19:23] – created rejeesh kutty | resources:eval:user-guides:ad-fmcadc7-ebz [17 Nov 2015 14:56] – [Downloads (Hardware)] michael gibson | ||
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===== Introduction ===== | ===== Introduction ===== | ||
- | The [[adi> | ||
- | |||
- | Although this board does meet most of the FMC specifications, | ||
ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards. | ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards. | ||
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===== Hardware ===== | ===== Hardware ===== | ||
- | The AD-FMCADC4-EBZ board' | + | The AD-FMCADC7-EBZ board' |
==== Devices ==== | ==== Devices ==== | ||
The FMC board includes the following products by Analog Devices: | The FMC board includes the following products by Analog Devices: | ||
- | * [[adi>AD9680]] 14-bit dual channel ADC with sampling speeds of up to 1250 MSPS, with a [[adi>JESD204|JESD204B]] | + | * [[adi>ADR280ARTZ]] 1.2 V Ultralow Power High PSRR Voltage Reference |
- | * [[adi>ADA4961]] Low Distortion, 3.2 GHz, RF Digital Gain Amplifier. | + | * [[adi>AD9625BBPZ-2.5]] 12-Bit, 2.5 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter |
- | * [[adi>AD9528]] | + | * [[adi>ADL5567ACPZ]] 4.8 GHz Ultrahigh Dynamic Range, Dual Differential |
- | * [[adi>ADP2384]] 20 V, 4 A, Synchronous, Step-Down DC-to-DC | + | * [[adi>ADF4355-2BCPZ]] Microwave Wideband Synthesizer |
- | * [[adi>ADP7104]] is a 20V, 500mA, low noise, CMOS LDO | + | * [[adi>AD7291BCPZ]] 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor |
- | * [[adi>ADM7154]] 600 mA, Ultra Low Noise, High PSRR, RF Linear Regulator | + | * [[adi> |
- | * [[adi>ADM7172]] 6.5 V, 2 A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO | + | * [[adi>ADP7104ARDZ-R7]] 20 V, 500 mA, Low Noise, CMOS LDO |
- | * [[adi>ADP1741]] is a 2A, low Vin, low dropout, CMOS linear regulator | + | * [[adi>ADP1741ACPZ]] 2 A, Low VIN, Low Dropout |
+ | * [[adi>ADP2119ACPZ]] 2 A/1.25 A, 1.2 MHz, Synchronous, Step-Down DC-to-DC Regulator | ||
+ | * [[adi>ADP2442ACPZ]] 36 V,1 A, Synchronous, Step-Down, DC-to-DC Regulator with | ||
+ | * External Clock Synchronization | ||
| | ||
{{ : | {{ : | ||
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==== Clocking ==== | ==== Clocking ==== | ||
- | The AD-FMCADC4-EBZ includes | + | The AD-FMCADC7-EBZ includes |
+ | - 2.5GHz Crystek | ||
+ | - An external reference | ||
+ | - 122.88MHz Crystek on-board oscillator differential or single ended to the ADF4355-2 | ||
+ | - An external reference supplied to J301 that would be provided to the ADF4355-2 | ||
==== Analog Front End ==== | ==== Analog Front End ==== | ||
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The revision A board supports amplifier gain control via spi. After power-up, the gain of the amplifier defaults to an attenuated state. Use a low jitter, low noise signal source with a level at -20dBm to the analog inputs (J301-A/ | The revision A board supports amplifier gain control via spi. After power-up, the gain of the amplifier defaults to an attenuated state. Use a low jitter, low noise signal source with a level at -20dBm to the analog inputs (J301-A/ | ||
- | ===== Running No-OS Application & Changing Sampling Rate to 1.24GHz ===== | + | ==== Revision B ==== |
- | The HDL reference design is built around a processor as in an embedded system. You may use either Linux or No-OS software to demonstrate the design (details in the downloads section). In order to run the HDL with the No-OS application, | + | The revision B board |
- | At the time of this writing, we are using the ' | ||
- | |||
- | Once the bit file is ready, follow these instructions to build the elf file. This assumes you are following our directory structures. If you are not, just get the idea from here and port it to your environment. However you have to figure out things on your own. | ||
- | |||
- | - Clone [[https:// | ||
- | - Checkout the ' | ||
- | - Change the directory to `ad-fmcadc4-ebz/ | ||
- | - Make the elf file by running `make HDF-FILE=< | ||
- | |||
- | The make will build the default ' | ||
- | |||
- | A typical run looks like this: | ||
- | |||
- | < | ||
- | [~/ | ||
- | xsct -s ../ | ||
- | |||
- | arm-xilinx-eabi-gcc -DXILINX -Ibsp/ | ||
- | [~/ | ||
- | </ | ||
- | |||
- | Start an UART terminal. | ||
- | |||
- | < | ||
- | [USB0] | ||
- | port = / | ||
- | speed = 115200 | ||
- | bits = 8 | ||
- | stopbits = 1 | ||
- | parity = none | ||
- | crlfauto = True ## if not set, expect non-aligned text | ||
- | |||
- | [~/ | ||
- | </ | ||
- | |||
- | The folder contains a zc706.tcl file that you can launch with xmd. You can also run it using Vivado or SDK - up to you. | ||
- | |||
- | < | ||
- | [~/ | ||
- | rlwrap: warning: your $TERM is ' | ||
- | |||
- | ****** Xilinx Microprocessor Debugger (XMD) Engine | ||
- | ****** XMD v2015.2 (64-bit) | ||
- | **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 | ||
- | ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. | ||
- | |||
- | Executing user script : zc706.tcl | ||
- | Configuring Device 2 (xc7z045) with Bitstream -- hw/ | ||
- | ....................10...................20...................30....................40...................50...................60....................70...................80...................90....................Done | ||
- | Successfully downloaded bit file. | ||
- | |||
- | JTAG chain configuration | ||
- | -------------------------------------------------- | ||
- | Device | ||
- | | ||
- | | ||
- | |||
- | |||
- | JTAG chain configuration | ||
- | -------------------------------------------------- | ||
- | Device | ||
- | | ||
- | | ||
- | |||
- | -------------------------------------------------- | ||
- | Enabling extended memory access checks for Zynq. | ||
- | Writes to reserved memory are not permitted and reads return 0. | ||
- | To disable this feature, run " | ||
- | |||
- | -------------------------------------------------- | ||
- | |||
- | CortexA9 Processor Configuration | ||
- | ------------------------------------- | ||
- | Version.............................0x00000003 | ||
- | User ID.............................0x00000000 | ||
- | No of PC Breakpoints................6 | ||
- | No of Addr/Data Watchpoints.........4 | ||
- | |||
- | Connected to " | ||
- | Starting GDB server for " | ||
- | Processor stopped | ||
- | |||
- | Processor Reset .... DONE | ||
- | Downloading Program -- zc706.elf | ||
- | section, .text: 0x00100000-0x0010656b | ||
- | section, .init: 0x0010656c-0x00106583 | ||
- | section, .fini: 0x00106584-0x0010659b | ||
- | section, .rodata: 0x0010659c-0x00106927 | ||
- | section, .data: 0x00106928-0x00106e9b | ||
- | section, .eh_frame: 0x00106e9c-0x00106e9f | ||
- | section, .mmu_tbl: 0x00108000-0x0010bfff | ||
- | section, .ARM.exidx: 0x0010c000-0x0010c007 | ||
- | section, .init_array: | ||
- | section, .fini_array: | ||
- | section, .bss: 0x0010c014-0x0010c0a7 | ||
- | section, .heap: 0x0010c0a8-0x0010e0af | ||
- | section, .stack: 0x0010e0b0-0x001118af | ||
- | Download Progress..10.20.30.40.50.60.70.80.90.Done | ||
- | Setting PC with Program Start Address 0x00100000 | ||
- | Processor started. Type " | ||
- | |||
- | RUNNING> Disconnected from Target 64 | ||
- | |||
- | Disconnected from Target 352 | ||
- | </ | ||
- | |||
- | The following messages should appear on the terminal. | ||
- | |||
- | < | ||
- | AD9528 successfully initialized. | ||
- | AD9680 PLL is locked. | ||
- | AD9680 successfully initialized. | ||
- | AD9680 PLL is locked. | ||
- | AD9680 successfully initialized. | ||
- | JESD204B successfully initialized. | ||
- | ADC Core Initialized (1000 MHz). | ||
- | ADC Core Initialized (1000 MHz). | ||
- | Initialization done. | ||
- | |||
- | Capture done. | ||
- | </ | ||
- | |||
- | A brief background information on what is happening. Let's look at the No-OS main function. | ||
- | First, it configures and sets the GPIO based on the board. | ||
- | |||
- | < | ||
- | adc4_gpio_ctl(GPIO_DEVICE_ID); | ||
- | </ | ||
- | |||
- | The clock chip is programmed to output the desired clocks and sys-ref signals. The default setting is 1GHz for the AD9680 and 500MHz for the FPGA. | ||
- | |||
- | < | ||
- | ad9528_setup(SPI_DEVICE_ID, | ||
- | </ | ||
- | |||
- | The transceiver cores are initialized. Here only DRP access is possible. If you are planning to change the transceivers, | ||
- | |||
- | < | ||
- | jesd204b_gt_initialize(FMCADC4_GT_BASEADDR, | ||
- | </ | ||
- | |||
- | The AD9680 devices are initialized (checking the PLL status) | ||
- | |||
- | < | ||
- | ad9680_setup(SPI_DEVICE_ID, | ||
- | ad9680_setup(SPI_DEVICE_ID, | ||
- | </ | ||
- | |||
- | The design uses Xilinx' | ||
- | |||
- | < | ||
- | jesd204b_setup(AD9680_JESD_BASEADDR, | ||
- | </ | ||
- | |||
- | After the above setup, bring the transceivers up, here we check for everything on the link, starting from the PLL locked to SYNC deasserted. | ||
- | |||
- | < | ||
- | | ||
- | </ | ||
- | |||
- | The individual AD9680 cores are brought out of reset. | ||
- | |||
- | < | ||
- | adc_setup(ad9680_0, | ||
- | adc_setup(ad9680_1, | ||
- | </ | ||
- | |||
- | The ADC has a PRBS generator at the sample level that can be monitored in the FPGA. This is a robust way to confirming the link status. The software monitors this and reports any errors. | ||
- | |||
- | This is setting the PRBS generator in the device. | ||
- | |||
- | < | ||
- | ad9680_spi_write(1, | ||
- | | ||
- | | ||
- | ad9680_spi_write(2, | ||
- | ad9680_spi_write(2, | ||
- | ad9680_spi_write(2, | ||
- | </ | ||
- | |||
- | This is setting the PRBS monitors in the FPGA. | ||
- | |||
- | < | ||
- | adc_pn_mon(ad9680_0, | ||
- | adc_pn_mon(ad9680_1, | ||
- | </ | ||
- | |||
- | If you don't see any other messages in the UART other than the ones mentioned above- all is well. You can open up Vivado and see things in ILA also. | ||
- | |||
- | Let's see now how we can change the sampling rate to 1.24 GHz. The AD9680 maximum sampling rate is 1.25GHz. However the board uses a 80MHz crystal as the reference clock to AD9528. Unless you change it, this limits the maximum clock output on the banks to 1.24GHz. Also note that the Kintex 7 SOC on ZC706 is a -2 device. The maximum lane rate is limited to 10Gbps. However, it should be possible to over clock the transceiver (but do so at your own risk). Officially, you must get a -3 device to run the link at 12.4Gbps. | ||
- | |||
- | Going back to our program. | ||
- | |||
- | < | ||
- | #ifdef MODE_1_24G | ||
- | ad9528_pdata_lpc.pll2_ndiv_a_cnt = 1; | ||
- | ad9528_pdata_lpc.pll2_ndiv_b_cnt = 23; | ||
- | ad9528_pdata_lpc.pll2_n2_div = 31; | ||
- | ad9528_pdata_lpc.pll2_vco_diff_m1 = 3; | ||
- | #endif | ||
- | </ | ||
- | |||
- | Let's define that macro somewhere on that file. | ||
- | |||
- | < | ||
- | [~/ | ||
- | 71a72 | ||
- | > #define MODE_1_24G | ||
- | </ | ||
- | |||
- | And re-run the make. | ||
- | |||
- | < | ||
- | [~/ | ||
- | arm-xilinx-eabi-gcc -DXILINX -Ibsp/ | ||
- | </ | ||
- | |||
- | The UART should now show this. | ||
- | |||
- | < | ||
- | AD9528 successfully initialized. | ||
- | AD9680 PLL is locked. | ||
- | AD9680 successfully initialized. | ||
- | AD9680 PLL is locked. | ||
- | AD9680 successfully initialized. | ||
- | JESD204B successfully initialized. | ||
- | ADC Core Initialized (1240 MHz). | ||
- | ADC Core Initialized (1240 MHz). | ||
- | Initialization done. | ||
- | |||
- | Capture done. | ||
- | </ | ||
- | |||
- | The clocks reported by the core is 1240MHz instead of the previous 1000MHz. There are no error messages and PRBS locks. This is all there is to it. There is no need for HDL modifications. However, if you ran into trouble here are a couple of things to try. | ||
- | |||
- | * If you have ran this back to back- try running 1.24GHz option from power up. | ||
- | * Modify the HDL to use a -3 device and change the constraints to run at 12.40Gbps | ||
- | * Upgrade the device on board to a -3 device. | ||
- | |||
- | Here is the UART window screen capture. | ||
- | |||
- | {{: | ||
- | |||
- | The application leaves the device in a ramp pattern, and if you are looking at the data using ILA should see it. If you would like to switch it to the analog input, do the following. In this case I am changing only the fourth channel (SMA - J301D). | ||
- | |||
- | < | ||
- | ad9680_spi_write(1, | ||
- | ad9680_spi_write(1, | ||
- | ad9680_spi_write(1, | ||
- | |||
- | ad9680_spi_write(2, | ||
- | ad9680_spi_write(2, | ||
- | ad9680_spi_write(2, | ||
- | |||
- | ad9680_spi_write(2, | ||
- | ad9680_spi_write(2, | ||
- | ad9680_spi_write(2, | ||
- | adc_write(ad9680_1, | ||
- | </ | ||
- | |||
- | Here is the ILA plot screen capture. | ||
- | |||
- | {{: | ||
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<WRAP download> | <WRAP download> | ||
+ | *****these links are incorrect | ||
Rev A: | Rev A: | ||
* {{: | * {{: | ||
Line 321: | Line 62: | ||
* {{: | * {{: | ||
* {{: | * {{: | ||
+ | Rev B: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | |||
</ | </ | ||