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| resources:eval:user-guides:ad-fmcadc7-ebz [17 Nov 2015 14:43] – [Devices] michael gibson | resources:eval:user-guides:ad-fmcadc7-ebz [03 Feb 2016 17:00] – Rob Reeder |
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| ===== Introduction ===== | ===== Introduction ===== |
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| | The [[adi>AD-FMCADC7-EBZ]] is a high speed single channel data acquisition board featuring the [[adi>AD9625]] a single channel differential Analog-to-Digital converter at 2.5 GHz and an [[adi>ADL5567]] dual channel differential 4.8 GHz amplifier. This is an FMC compatible board. The clocking can be done three different ways including external variations and on-board variations with Crystek oscillator and an [[adi>ADF4355-2]]. |
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| ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards. | ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards. |
| ===== Hardware ===== | ===== Hardware ===== |
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| The AD-FMCADC-EBZ board's primary purpose is to demonstrate the capabilities of the devices on board quickly and easily by providing a seamless interface to an FMC carrier platform and running the reference design on the carrier FPGA. The board is designed to self power and self clock when connected to the FMC carrier. The analog signals ( AIN+ and AIN-) are connected to J202 and J201. This rapid prototyping board is default set up with a dc coupled input path. | The AD-FMCADC7-EBZ board's primary purpose is to demonstrate the capabilities of the devices on board quickly and easily by providing a seamless interface to an FMC carrier platform and running the reference design on the carrier FPGA. The board is designed to self power and self clock when connected to the FMC carrier. The analog signals ( AIN+ and AIN-) are connected to J202 and J201. This rapid prototyping board is default set up with to utilize input J202 for a single-ended connection from a signal generator. |
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| ==== Devices ==== | ==== Devices ==== |
| * External Clock Synchronization | * External Clock Synchronization |
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| {{ :resources:eval:user-guides:20150331_135648-final.jpg?nolink&300 |}} | {{ :resources:eval:user-guides:fmcadc7-top.jpg?nolink&200 |}} |
| Top View | Top View |
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| {{ :resources:eval:user-guides:20150402_100228-finalbot.jpg?nolink&300 |}} | {{ :resources:eval:user-guides:fmcadc7-bot.jpg?nolink&200 |}} |
| Bottom View | Bottom View |
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| ==== Clocking ==== | ==== Clocking ==== |
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| The AD-FMCADC4-EBZ includes an on-board 80MHz reference oscillator from Crystek. This feature can be disconnected and an external reference can be applied through J901. When referencing the schematic make sure the proper component changes are made in order to directly route the input into the AD9528. | The AD-FMCADC7-EBZ includes various clocking options: |
| | - 2.5GHz Crystek on-board oscillator, Y401, to a differential balun which connects directly to the converter's clock input pins. |
| | - An external reference supplied at J301 to use in conjunction with the ADF4355-2. |
| | - 122.88MHz Crystek on-board oscillator reference to the ADF4355-2 |
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| ==== Analog Front End ==== | ==== Analog Front End ==== |
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| The AD-FMCADC4-EBZ uses a passive front end designed for very wide bandwidth. A single ended input needs to be provided to the analog inputs mentioned earlier. A 1:2 impedance ratio broadband balun then converts the input signal differentially to the ADA4961 inputs and has a 1.6GHz bandwidth at -3dB. Each channel amplifier can be adjusted independently in terms of gain. | The AD-FMCADC7-EBZ uses a active front end designed for very wide bandwidth. A single ended input needs to be provided to the analog inputs at -15dBm. The broadband amplifier gains and converts the analog input signal deferentially to the converter's inputs and has a 1.8GHz bandwidth at -3dB. The amplifier's gain can be adjusted independently with some simple resistor modifications. |
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| ==== Revision A ==== | |
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| The revision A board supports amplifier gain control via spi. After power-up, the gain of the amplifier defaults to an attenuated state. Use a low jitter, low noise signal source with a level at -20dBm to the analog inputs (J301-A/B/C/D). Apply a signal source no greater than -10dBm to achieve full-scale of the converter when maximum gain of the amplifier is applied. | ==== Revision B ==== |
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| | The revision B board is default set for the amplifier to be at max gain with dc coupling. Hardware changes are required to change either the gain or dc coupling to ac coupling. |
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| <WRAP download> | <WRAP download> |
| Rev A: | |
| * {{:undefined:ska_eval-08212014.pdf| Schematic}} | |
| * {{:resources:eval:user-guides:ska_bom-03172015.xlsx| Bill of Materials}} | |
| * {{:resources:eval:user-guides:ska_eval_fab.pdf| PCBoard Fab Drawing}} | |
| * {{:resources:eval:user-guides:ska_eval_cam2.zip| PCBoard Gerber files}} | |
| </WRAP> | |
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| ===== Downloads (HDL) ===== | Rev B: |
| | * {{:resources:eval:user-guides:20_040403b_artwork.zip|}}| Gerber files}} |
| | * {{:resources:eval:user-guides:ad_fmcadcv7b.pdf| Schematic}} |
| | * {{:resources:eval:user-guides:ad-fmcadcv7b-ebz_bom-12142015-final.xls| Bill of Materials}} |
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| {{page>/resources/fpga/docs/hdl/downloads_insert#fmcadc4&nofooter&noeditbtn}} | </WRAP> |
| {{page>/resources/fpga/docs/hdl/downloads_insert#help_support&nofooter&noeditbtn}} | |
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| ===== Downloads (Linux) ===== | |
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| * [[/resources/tools-software/linux-drivers/iio-adc/axi-jesd204b-hdl|JESD Linux Driver]] | |
| * [[/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl|AD9680-ADA4961 Linux driver]] | |
| * [[/resources/tools-software/linux-software/zynq_images|ZC706 Linux image]] | |
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