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resources:eval:user-guides:ad-fmcadc7-ebz [16 Nov 2015 19:45]
michael gibson
resources:eval:user-guides:ad-fmcadc7-ebz [02 Feb 2016 22:01]
Rob Reeder
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 ===== Introduction ===== ===== Introduction =====
  
 +The [[adi>​AD-FMCADC7-EBZ]] is a high speed single channel data acquisition board featuring the [[adi>​AD9625]] a single channel differential Analog-to-Digital converter at 2.5 GHz and an [[adi>​ADL5567]] dual channel differential 4.8 GHz amplifier. This is an FMC compatible board. The clocking can be done four different ways including external variations and on-board variations with Crystek oscillators and an [[adi>​ADF4355-2]].
  
 ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards. ​ ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards. ​
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 ===== Hardware ===== ===== Hardware =====
  
-The AD-FMCADC4-EBZ board'​s primary purpose is to demonstrate the capabilities of the devices on board quickly and easily by providing a seamless interface to an FMC carrier platform and running the reference design on the carrier FPGA. The board is designed to self power and self clock when connected to the FMC carrier. The analog signals (up to four) are connected to J301A, J301B, J301C and J301D. This rapid prototyping board can also be synchronized across channels.+The AD-FMCADC7-EBZ board'​s primary purpose is to demonstrate the capabilities of the devices on board quickly and easily by providing a seamless interface to an FMC carrier platform and running the reference design on the carrier FPGA. The board is designed to self power and self clock when connected to the FMC carrier. The analog signals ( AIN+ and AIN-) are connected to J202 and J201. This rapid prototyping board is default set up with to utilize port J202.
  
 ==== Devices ==== ==== Devices ====
  
 The FMC board includes the following products by Analog Devices: The FMC board includes the following products by Analog Devices:
-  * [[adi>AD9680]] 14-bit dual channel ADC with sampling speeds of up to 1250 MSPS, with a [[adi>JESD204|JESD204B]]  ​digital interface+  * [[adi>ADR280ARTZ]] 1.2 V Ultralow Power High PSRR Voltage Reference 
-  * [[adi>ADA4961]]  Low Distortion, 3.GHz, RF Digital Gain Amplifier. +  * [[adi>AD9625BBPZ-2.5]] 12-Bit, 2.5 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter 
-  * [[adi>AD9528]]  ​JESD204B Clock Generator ​with 14 LVDS Outputs +  * [[adi>ADL5567ACPZ]] 4.GHz Ultrahigh Dynamic RangeDual Differential ​Amplifier 
-  * [[adi>ADP2384]] 20 VA, SynchronousStep-Down DC-to-DC ​Regulator +  * [[adi>ADF4355-2BCPZ]] Microwave Wideband Synthesizer ​with Integrated VCO 
-  * [[adi>ADP7104]] is a 20V500mAlow noise, CMOS LDO +  * [[adi>AD7291BCPZ]] 8-ChannelI2C, 12-Bit SAR ADC with Temperature Sensor 
-  * [[adi>ADM7154]] 600 mAUltra Low NoiseHigh PSRR, RF Linear Regulator +  * [[adi>​ADP1753ACPZ]] 0.8 A, Low VINLow Dropout Linear ​Regulator 
-  * [[adi>ADM7172]]  6.5 V, 2 AUltralow NoiseHigh PSRR, Fast Transient Response CMOS LDO +  * [[adi>ADP7104ARDZ-R7]] 20 V500 mALow Noise, CMOS LDO 
-  * [[adi>ADP1741]] is a 2Alow Vinlow dropoutCMOS linear regulator+  * [[adi>ADP1741ACPZ]] 2 A, Low VINLow Dropout ​Linear Regulator 
 +  * [[adi>ADP2119ACPZ]] 2 A/1.25 A1.MHzSynchronousStep-Down DC-to-DC Regulator 
 +  * [[adi>ADP2442ACPZ]] 36 V,1 ASynchronousStep-Down, DC-to-DC Regulator with  
 +          * External Clock Synchronization
   ​   ​
-{{ :​resources:​eval:​user-guides:​20150331_135648-final.jpg?​nolink&​300 |}}+{{ :​resources:​eval:​user-guides:​fmcadc7-top.jpg?​nolink&​200 |}}
                                                    Top View                                                    Top View
  
-{{ :​resources:​eval:​user-guides:​20150402_100228-finalbot.jpg?​nolink&​300 |}}+{{ :​resources:​eval:​user-guides:​fmcadc7-bot.jpg?​nolink&​200 |}}
                                                    ​Bottom View                                                    ​Bottom View
  
 ==== Clocking ==== ==== Clocking ====
  
-The AD-FMCADC4-EBZ includes ​an on-board ​80MHz reference ​oscillator ​from Crystek. This feature can be disconnected and an external reference ​can be applied through J901When referencing the schematic make sure the proper component changes are made in order to directly route the input into the AD9528.+The AD-FMCADC7-EBZ includes ​various clocking options: 
 +      - 2.5GHz Crystek ​on-board oscillator ​to a differential balun 
 +      - An external reference ​supplied at J401 
 +      - 122.88MHz Crystek on-board oscillator differential or single ended to the ADF4355-2 
 +      - An external reference supplied to J301 that would be provided ​to the ADF4355-2
  
 ==== Analog Front End ==== ==== Analog Front End ====
  
-The AD-FMCADC4-EBZ uses a passive ​front end designed for very wide bandwidth. ​ A single ended input needs to be provided to the analog inputs mentioned earlier.  ​A 1:2 impedance ratio broadband ​balun then converts the input signal differentially to the ADA4961 ​inputs and has a 1.6GHz bandwidth at -3dB. Each channel ​amplifier can be adjusted independently ​in terms of gain.+The AD-FMCADC7-EBZ uses a active ​front end designed for very wide bandwidth. ​ A single ended input needs to be provided to the analog inputs mentioned earlier.  ​The broadband ​amplifier ​then converts the input signal differentially to the converter'​s ​inputs and has a 1.8GHz bandwidth at -3dB. The amplifier's gain can be adjusted independently ​with some simple resistor modifications.
  
-==== Revision A ==== 
  
-The revision A board supports amplifier gain control via spi. After power-up, the gain of the amplifier defaults to an attenuated state. Use a low jitter, low noise signal source with a level at -20dBm to the analog inputs (J301-A/B/C/D). Apply a signal source no greater than -10dBm to achieve full-scale of the converter when maximum gain of the amplifier is applied. ​+==== Revision ​====
  
-===== Running No-OS Application & Changing Sampling Rate to 1.24GHz =====+The revision B board is default set for the amplifier ​to be at max gain with dc couplingHardware changes are required to change either the gain or dc coupling to ac coupling.  ​
  
-The HDL reference design is built around a processor as in an embedded system. You may use either Linux or No-OS software to demonstrate the design (details in the downloads section). In order to run the HDL with the No-OS application,​ one need to build the HDL bit file and software elf file. 
- 
-At the time of this writing, we are using the '​dev'​ branch for both. The [[https://​wiki.analog.com/​resources/​fpga/​docs/​hdl|HDL user guide]] contains the instructions to build the bit file. **Please make sure you use the '​dev'​ branch (checkout dev right after cloning).** 
- 
-Once the bit file is ready, follow these instructions to build the elf file. This assumes you are following our directory structures. If you are not, just get the idea from here and port it to your environment. However you have to figure out things on your own. 
- 
-  - Clone [[https://​github.com/​analogdevicesinc/​no-OS|No-OS]] repository 
-  - Checkout the '​dev'​ branch (git checkout dev) 
-  - Change the directory to `ad-fmcadc4-ebz/​zc706`. 
-  - Make the elf file by running `make HDF-FILE=<​HDL-REPO>/​projects/​fmcadc4/​zc706/​fmcadc4_zc706.sdk/​system_top.hdf` 
- 
-The make will build the default '​hello-world',​ but we only need the bsp and I am no fan of eclipse, hence this method. If you are more comfortable with the GUI, import all the files (or folders) that the make uses. 
- 
-A typical run looks like this: 
- 
-<​xterm>​ 
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]>​ make HDF-FILE=~/​github/​hdl/​projects/​fmcadc4/​zc706/​fmcadc4_zc706.sdk/​system_top.hdf ​ 
-xsct -s ../​../​scripts/​xilinx_xsct.tcl ~/​github/​hdl/​projects/​fmcadc4/​zc706/​fmcadc4_zc706.sdk/​system_top.hdf >> xilinx_xsct.log 2>&1 
-                                                                                                                                                                                                  
-arm-xilinx-eabi-gcc -DXILINX -Ibsp/​ps7_cortexa9_0/​include -I.. -I../​../​common_drivers/​adc_core -I../​../​common_drivers/​jesd204b_gt -I../​../​common_drivers/​jesd204b_v51 -I../​../​common_drivers/​xilinx_platform_drivers -I../​../​drivers/​ad9528 -I../​../​drivers/​ad9680 -Os -ffunction-sections -fdata-sections -o zc706.elf sw/​src/​platform.c ../​ad_fmcadc4_ebz.c ../​../​common_drivers/​adc_core/​adc_core.c ../​../​common_drivers/​jesd204b_gt/​jesd204b_gt.c ../​../​common_drivers/​jesd204b_v51/​jesd204b_v51.c ../​../​common_drivers/​xilinx_platform_drivers/​platform_drivers.c ../​../​drivers/​ad9528/​ad9528.c ../​../​drivers/​ad9680/​ad9680.c -Lbsp/​ps7_cortexa9_0/​lib/​ -Tsw/​src/​lscript.ld -Wl,​--start-group,​-lxil,​-lgcc,​-lc,​--end-group 
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706] 
-</​xterm>​ 
- 
-Start an UART terminal. 
- 
-<​xterm>​ 
-[USB0] 
-port = /​dev/​ttyUSB0 
-speed = 115200 
-bits = 8 
-stopbits = 1 
-parity = none 
-crlfauto = True ## if not set, expect non-aligned text 
- 
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]>​ gtkterm -c USB0 & 
-</​xterm>​ 
- 
-The folder contains a zc706.tcl file that you can launch with xmd. You can also run it using Vivado or SDK - up to you. 
- 
-<​xterm>​ 
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]>​ xmd -tcl zc706.tcl ​ 
-rlwrap: warning: your $TERM is '​xterm'​ but rlwrap couldn'​t find it in the terminfo database. Expect some problems. 
-                                                                                                                                                                                                  
-****** Xilinx Microprocessor Debugger (XMD) Engine 
-****** XMD v2015.2 (64-bit) 
-  **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 
-    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. 
- 
-Executing user script : zc706.tcl 
-Configuring Device 2 (xc7z045) with Bitstream -- hw/​system_top.bit ​                                                                                                                               
-....................10...................20...................30....................40...................50...................60....................70...................80...................90....................Done 
-Successfully downloaded bit file. 
- 
-JTAG chain configuration 
--------------------------------------------------- 
-Device ​  ID Code        IR Length ​   Part Name 
- ​1 ​      ​4ba00477 ​          ​4 ​       arm_dap 
- ​2 ​      ​23731093 ​          ​6 ​       xc7z045 
- 
- 
-JTAG chain configuration 
--------------------------------------------------- 
-Device ​  ID Code        IR Length ​   Part Name 
- ​1 ​      ​4ba00477 ​          ​4 ​       arm_dap 
- ​2 ​      ​23731093 ​          ​6 ​       xc7z045 
- 
--------------------------------------------------- 
-Enabling extended memory access checks for Zynq. 
-Writes to reserved memory are not permitted and reads return 0. 
-To disable this feature, run "​debugconfig -memory_access_check disable"​. 
- 
--------------------------------------------------- 
- 
-CortexA9 Processor Configuration 
-------------------------------------- 
-Version.............................0x00000003 
-User ID.............................0x00000000 
-No of PC Breakpoints................6 
-No of Addr/Data Watchpoints.........4 
- 
-Connected to "​arm"​ target. id = 64 
-Starting GDB server for "​arm"​ target (id = 64) at TCP port no 1234 
-Processor stopped 
- 
-Processor Reset .... DONE                                                                                                                                                                        ​ 
-Downloading Program -- zc706.elf 
-        section, .text: 0x00100000-0x0010656b 
-        section, .init: 0x0010656c-0x00106583 
-        section, .fini: 0x00106584-0x0010659b 
-        section, .rodata: 0x0010659c-0x00106927 
-        section, .data: 0x00106928-0x00106e9b 
-        section, .eh_frame: 0x00106e9c-0x00106e9f 
-        section, .mmu_tbl: 0x00108000-0x0010bfff 
-        section, .ARM.exidx: 0x0010c000-0x0010c007 
-        section, .init_array:​ 0x0010c008-0x0010c00f 
-        section, .fini_array:​ 0x0010c010-0x0010c013 
-        section, .bss: 0x0010c014-0x0010c0a7 
-        section, .heap: 0x0010c0a8-0x0010e0af 
-        section, .stack: 0x0010e0b0-0x001118af 
-Download Progress..10.20.30.40.50.60.70.80.90.Done 
-Setting PC with Program Start Address 0x00100000 
-Processor started. Type "​stop"​ to stop processor 
- 
-RUNNING> Disconnected from Target 64 
- 
-Disconnected from Target 352 
-</​xterm>​ 
- 
-The following messages should appear on the terminal. 
- 
-<​xterm>​ 
-AD9528 successfully initialized. 
-AD9680 PLL is locked. 
-AD9680 successfully initialized. 
-AD9680 PLL is locked. 
-AD9680 successfully initialized. 
-JESD204B successfully initialized. 
-ADC Core Initialized (1000 MHz). 
-ADC Core Initialized (1000 MHz). 
-Initialization done. 
- 
-Capture done. 
-</​xterm>​ 
- 
-A brief background information on what is happening. Let's look at the No-OS main function. 
-First, it configures and sets the GPIO based on the board. 
- 
-<​xterm>​ 
- adc4_gpio_ctl(GPIO_DEVICE_ID);​ 
-</​xterm>​ 
- 
-The clock chip is programmed to output the desired clocks and sys-ref signals. The default setting is 1GHz for the AD9680 and 500MHz for the FPGA. 
- 
-<​xterm>​ 
- ad9528_setup(SPI_DEVICE_ID,​ 0, ad9528_pdata_lpc);​ 
-</​xterm>​ 
- 
-The transceiver cores are initialized. Here only DRP access is possible. If you are planning to change the transceivers,​ this is where they should be. 
- 
-<​xterm>​ 
- jesd204b_gt_initialize(FMCADC4_GT_BASEADDR,​ 8); 
-</​xterm>​ 
- 
-The AD9680 devices are initialized (checking the PLL status) 
- 
-<​xterm>​ 
- ad9680_setup(SPI_DEVICE_ID,​ 1); 
- ad9680_setup(SPI_DEVICE_ID,​ 2); 
-</​xterm>​ 
- 
-The design uses Xilinx'​s JESD IP- it needs to be programmed to match the device settings (frame count, byte count, scrambling and such). 
- 
-<​xterm>​ 
- jesd204b_setup(AD9680_JESD_BASEADDR,​ jesd204b_st);​ 
-</​xterm>​ 
- 
-After the above setup, bring the transceivers up, here we check for everything on the link, starting from the PLL locked to SYNC deasserted. 
- 
-<​xterm>​ 
- ​ jesd204b_gt_setup(ad9680_gt_link);​ 
-</​xterm>​ 
- 
-The individual AD9680 cores are brought out of reset. 
- 
-<​xterm>​ 
- adc_setup(ad9680_0,​ 2); 
- adc_setup(ad9680_1,​ 2); 
-</​xterm>​ 
- 
-The ADC has a PRBS generator at the sample level that can be monitored in the FPGA. This is a robust way to confirming the link status. The software monitors this and reports any errors. 
- 
-This is setting the PRBS generator in the device. 
- 
-<​xterm>​ 
- ad9680_spi_write(1,​ AD9680_REG_DEVICE_INDEX,​ 0x3); 
- ​ ad9680_spi_write(1,​ AD9680_REG_ADC_TEST_MODE,​ 0x05); 
- ​ ad9680_spi_write(1,​ AD9680_REG_OUTPUT_MODE,​ 0); 
- ad9680_spi_write(2,​ AD9680_REG_DEVICE_INDEX,​ 0x3); 
- ad9680_spi_write(2,​ AD9680_REG_ADC_TEST_MODE,​ 0x05); 
- ad9680_spi_write(2,​ AD9680_REG_OUTPUT_MODE,​ 0); 
-</​xterm>​ 
- 
-This is setting the PRBS monitors in the FPGA. 
- 
-<​xterm>​ 
- adc_pn_mon(ad9680_0,​ 2, 1); 
- adc_pn_mon(ad9680_1,​ 2, 1); 
-</​xterm>​ 
- 
-If you don't see any other messages in the UART other than the ones mentioned above- all is well. You can open up Vivado and see things in ILA also. 
- 
-Let's see now how we can change the sampling rate to 1.24 GHz. The AD9680 maximum sampling rate is 1.25GHz. However the board uses a 80MHz crystal as the reference clock to AD9528. Unless you change it, this limits the maximum clock output on the banks to 1.24GHz. Also note that the Kintex 7 SOC on ZC706 is a -2 device. The maximum lane rate is limited to 10Gbps. However, it should be possible to over clock the transceiver (but do so at your own risk). Officially, you must get a -3 device to run the link at 12.4Gbps. 
- 
-Going back to our program. 
- 
-<​xterm>​ 
-#ifdef MODE_1_24G 
- ad9528_pdata_lpc.pll2_ndiv_a_cnt = 1; 
- ad9528_pdata_lpc.pll2_ndiv_b_cnt = 23; 
- ad9528_pdata_lpc.pll2_n2_div = 31; 
- ad9528_pdata_lpc.pll2_vco_diff_m1 = 3; 
-#endif 
-</​xterm>​ 
- 
-Let's define that macro somewhere on that file. 
- 
-<​xterm>​ 
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]>​ gitdiff.pl ../​ad_fmcadc4_ebz.c ​ 
-71a72 
-> #define MODE_1_24G 
-</​xterm>​ 
- 
-And re-run the make. 
- 
-<​xterm>​ 
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]>​ make HDF-FILE=~/​github/​hdl/​projects/​fmcadc4/​zc706/​fmcadc4_zc706.sdk/​system_top.hdf ​ 
-arm-xilinx-eabi-gcc -DXILINX -Ibsp/​ps7_cortexa9_0/​include -I.. -I../​../​common_drivers/​adc_core -I../​../​common_drivers/​jesd204b_gt -I../​../​common_drivers/​jesd204b_v51 -I../​../​common_drivers/​xilinx_platform_drivers -I../​../​drivers/​ad9528 -I../​../​drivers/​ad9680 -Os -ffunction-sections -fdata-sections -o zc706.elf sw/​src/​platform.c ../​ad_fmcadc4_ebz.c ../​../​common_drivers/​adc_core/​adc_core.c ../​../​common_drivers/​jesd204b_gt/​jesd204b_gt.c ../​../​common_drivers/​jesd204b_v51/​jesd204b_v51.c ../​../​common_drivers/​xilinx_platform_drivers/​platform_drivers.c ../​../​drivers/​ad9528/​ad9528.c ../​../​drivers/​ad9680/​ad9680.c -Lbsp/​ps7_cortexa9_0/​lib/​ -Tsw/​src/​lscript.ld -Wl,​--start-group,​-lxil,​-lgcc,​-lc,​--end-group 
-</​xterm>​ 
- 
-The UART should now show this. 
- 
-<​xterm>​ 
-AD9528 successfully initialized. 
-AD9680 PLL is locked. 
-AD9680 successfully initialized. 
-AD9680 PLL is locked. 
-AD9680 successfully initialized. 
-JESD204B successfully initialized. 
-ADC Core Initialized (1240 MHz). 
-ADC Core Initialized (1240 MHz). 
-Initialization done. 
- 
-Capture done. 
-</​xterm>​ 
- 
-The clocks reported by the core is 1240MHz instead of the previous 1000MHz. There are no error messages and PRBS locks. This is all there is to it. There is no need for HDL modifications. However, if you ran into trouble here are a couple of things to try. 
- 
-  * If you have ran this back to back- try running 1.24GHz option from power up. 
-  * Modify the HDL to use a -3 device and change the constraints to run at 12.40Gbps 
-  * Upgrade the device on board to a -3 device. 
- 
-Here is the UART window screen capture. 
- 
-{{:​resources:​eval:​user-guides:​fmcadc4_uart.png?​400|FMCADC4-UART}} 
- 
-The application leaves the device in a ramp pattern, and if you are looking at the data using ILA should see it. If you would like to switch it to the analog input, do the following. In this case I am changing only the fourth channel (SMA - J301D). 
- 
-<​xterm>​ 
- ad9680_spi_write(1,​ AD9680_REG_DEVICE_INDEX,​ 0x3); 
- ad9680_spi_write(1,​ AD9680_REG_ADC_TEST_MODE,​ 0x0F); 
- ad9680_spi_write(1,​ AD9680_REG_OUTPUT_MODE,​ 0x1); 
- 
- ad9680_spi_write(2,​ AD9680_REG_DEVICE_INDEX,​ 0x3); 
- ad9680_spi_write(2,​ AD9680_REG_ADC_TEST_MODE,​ 0x0F); 
- ad9680_spi_write(2,​ AD9680_REG_OUTPUT_MODE,​ 0x1); 
- 
- ad9680_spi_write(2,​ AD9680_REG_DEVICE_INDEX,​ 0x2); 
- ad9680_spi_write(2,​ AD9680_REG_ADC_TEST_MODE,​ 0x00); 
- ad9680_spi_write(2,​ AD9680_REG_OUTPUT_MODE,​ 0x1); 
-        adc_write(ad9680_1,​ ADC_REG_CHAN_CNTRL(1),​ 0x51); 
-</​xterm>​ 
- 
-Here is the ILA plot screen capture. 
- 
-{{:​resources:​eval:​user-guides:​fmcadc4_ila.png?​500|FMCADC4-ILA}} 
  
  
Line 313: Line 55:
  
 <WRAP download>​ <WRAP download>​
-Rev A: 
-  * {{:​undefined:​ska_eval-08212014.pdf| Schematic}} 
-  * {{:​resources:​eval:​user-guides:​ska_bom-03172015.xlsx| Bill of Materials}} 
-  * {{:​resources:​eval:​user-guides:​ska_eval_fab.pdf| PCBoard Fab Drawing}} 
-  * {{:​resources:​eval:​user-guides:​ska_eval_cam2.zip| PCBoard Gerber files}} 
-</​WRAP>​ 
  
-===== Downloads (HDL) =====+Rev B: 
 +  * {{:​resources:​eval:​user-guides:​20_040403b_artwork.zip|}}| Gerber files}} 
 +  * {{:​resources:​eval:​user-guides:​ad_fmcadcv7b.pdf| Schematic}} 
 +  * {{:​resources:​eval:​user-guides:​ad-fmcadcv7b-ebz_bom-12142015-final.xls| Bill of Materials}}
  
-{{page>/resources/​fpga/​docs/​hdl/​downloads_insert#​fmcadc4&​nofooter&​noeditbtn}} +</WRAP>
-{{page>/​resources/​fpga/​docs/​hdl/​downloads_insert#​help_support&​nofooter&​noeditbtn}} +
- +
-===== Downloads (Linux) ===== +
- +
-  * [[/​resources/​tools-software/​linux-drivers/​iio-adc/​axi-jesd204b-hdl|JESD Linux Driver]] +
-  * [[/​resources/​tools-software/​linux-drivers/​iio-adc/​axi-adc-hdl|AD9680-ADA4961 Linux driver]] +
-  * [[/​resources/​tools-software/​linux-software/​zynq_images|ZC706 Linux image]]+
  
  
resources/eval/user-guides/ad-fmcadc7-ebz.txt · Last modified: 08 Jan 2021 08:54 by Ioana Chelaru