| Both sides previous revisionPrevious revisionNext revision | Previous revisionNext revisionBoth sides next revision |
| resources:eval:user-guides:ad-fmcadc5-ebz [06 Mar 2018 14:42] – changed the branch used Adrian Costina | resources:eval:user-guides:ad-fmcadc5-ebz [14 Feb 2019 10:21] – Fixed broken links Adrian Costina |
|---|
| |
| ===== Introduction ===== | ===== Introduction ===== |
| {{ :resources:eval:user-guides:ad-fmcadc5-ebz:ad-fmcadc5-ebz.jpg?400|}} The [[http://www.xilinx.com/products/boards-and-kits/1-5l1boj.html|AD-FMCADC5-EBZ]] is a high speed single channel data acquisition board featuring two [[adi>AD9625]] ADCs. The board is provisioned to sample the single input at an effective sampling rate of 5GSPS, with both the ADCs running at 2.5GHz and sampling at both edges (the clocks are 180 out of phase to each other). The board is a variant of [[http://www.fidus.com/analog-digital-converters|FSF-AD15000A]] from Fidus Systems Inc. | {{ :resources:eval:user-guides:ad-fmcadc5-ebz:ad-fmcadc5-ebz.jpg?400|}} The [[adi>AD-FMCADC5-EBZ|AD-FMCADC5-EBZ]] is a high speed single channel data acquisition board featuring two [[adi>AD9625]] ADCs. The board is provisioned to sample the single input at an effective sampling rate of 5GSPS, with both the ADCs running at 2.5GHz and sampling at both edges (the clocks are 180 out of phase to each other). The board is a variant of [[https://fidus.com/fmcs/|FSF-AD15000A]] from Fidus Systems Inc. |
| |
| Although this board does meet most of the FMC specifications, it is not meant as a [[wp>Commercial_off-the-shelf|commercial off the shelf]] (COTS) board. If a commercial, ready to go integrate product is required, please refer to one of the many FMC manufacturers. | Although this board does meet most of the FMC specifications, it is not meant as a [[wp>Commercial_off-the-shelf|commercial off the shelf]] (COTS) board. If a commercial, ready to go integrate product is required, please refer to one of the many FMC manufacturers. |
| |
| The AD-FMCADC5-EBZ uses a 2.5GHz crystal. The two AD9625 devices are clocked from the same clock source, but 180 degrees out of phase. | The AD-FMCADC5-EBZ uses a 2.5GHz crystal. The two AD9625 devices are clocked from the same clock source, but 180 degrees out of phase. |
| |
| ==== Analog Front End ==== | |
| |
| ===== Running No-OS Application & Achieving Interleaving at 5GSPS ===== | ===== Running No-OS Application & Achieving Interleaving at 5GSPS ===== |
| ==== Building & Running the No-OS Application ==== | ==== Building & Running the No-OS Application ==== |
| |
| The HDL reference design is built around a processor as in an embedded system. You may use either Linux or No-OS software to demonstrate the design (details in the downloads section). In order to run the HDL with the No-OS application, one need to build the HDL bit file and software elf file. | The HDL reference design is built around a processor as in an embedded system. You may use either Linux or No-OS software to demonstrate the design (details in the downloads section). In order to run the HDL with the No-OS application, one needs to build the HDL bit file and software elf file. |
| |
| The [[https://wiki.analog.com/resources/fpga/docs/hdl|HDL user guide]] contains the instructions to build the bit file. **Please make sure you use the latest release branch (checkout right after cloning).** | The [[https://wiki.analog.com/resources/fpga/docs/hdl|HDL user guide]] contains the instructions to build the bit file. **Please make sure you use the latest release branch (checkout right after cloning).** |
| |
| Once the bit file is ready, follow these instructions to build the elf file. This assumes you are following our directory structures. If you are not, just get the idea from here and port it to your environment. However you have to figure out things on your own. | Once the bit file is ready, follow these instructions to build the elf file. This assumes you are following our directory structures. If you are not, just get the idea from here and port it to your environment. However, you have to figure out things on your own. |
| |
| - Clone [[https://github.com/analogdevicesinc/no-OS|No-OS]] repository | - Clone [[https://github.com/analogdevicesinc/no-OS|No-OS]] repository |
| - Make the elf file by running `make HDF-FILE=<HDL-REPO>/projects/fmcadc5/vc707/fmcadc5_vc707.sdk/system_top.hdf` | - Make the elf file by running `make HDF-FILE=<HDL-REPO>/projects/fmcadc5/vc707/fmcadc5_vc707.sdk/system_top.hdf` |
| |
| The make will build the default 'hello-world', but we only need the bsp and I am no fan of eclipse, hence this method. If you are more comfortable with the GUI, import all the files (or folders) that the make uses. | The make will build the default 'hello-world', but we only need the bsp and I am no fan of eclipse, therefore this method. If you are more comfortable with the GUI, import all the files (or folders) that the make uses. |
| |
| A typical run looks like this: | A typical run looks like this: |
| A brief introduction to interleaving, everyone knows this but we will start with it anyway. We have two AD9625 devices running at 2.5Gbps, but the clocks to the devices are 180 degrees out of phase. In other words, the input signal is sampled by the first ADC at the rising edges of the 2.5GHz clock. The same signal is sampled by the second ADC at the falling edges of the "conceptually same" clock. That is an effective sampling rate of 5GSPS. All the user needs to do is interleave these two samples. That sounds easy, but there are some challenges. | A brief introduction to interleaving, everyone knows this but we will start with it anyway. We have two AD9625 devices running at 2.5Gbps, but the clocks to the devices are 180 degrees out of phase. In other words, the input signal is sampled by the first ADC at the rising edges of the 2.5GHz clock. The same signal is sampled by the second ADC at the falling edges of the "conceptually same" clock. That is an effective sampling rate of 5GSPS. All the user needs to do is interleave these two samples. That sounds easy, but there are some challenges. |
| |
| A word of caution (or disclaimer), this interleaving inherently has some performance factors outside of what we are discussing here. There are two major factors, first the jitter on the sampling clocks. Second, the gain and phase variations at the input. The devices itself may also have encoding skew. Some of these may be filtered or compensated by post processing the samples. I can not go into the details here, just keep in mind that we are not talking about these things. Here our focus is in understanding the FPGA design and how to achieve interleaving - not the performance effects. | A word of caution (or disclaimer), this interleaving inherently has some performance factors outside of what we are discussing here. There are two major factors, first the jitter on the sampling clocks. Second, the gain and phase variations at the input. The devices itself may also have encoding skew. Some of these may be filtered or compensated by post processing the samples. I can not go into the details here, just keep in mind that we are not talking about these things. Here our focus is on understanding the FPGA design and how to achieve interleaving - not the performance effects. |
| |
| {{ :resources:eval:user-guides:fmcadc5_intlv_hdl.png?800 |AD-FMCADC5-BD}} | {{ :resources:eval:user-guides:fmcadc5_intlv_hdl.png?800 |AD-FMCADC5-BD}} |
| If we look at the data path of the devices independently (see block diagram above), we can see that alignment and deskew happens at various stages. The transceivers perform deskew and alignment of bits (comma character alignment and 10B to 8B conversion), the JESD-IP then aligns individual lanes and outputs data with a fixed latency using SYSREF. The SYSREF resets the LMFC, thus the receiver knows from the time it receives the SYSREF pulse to the first received ILA data the latency of the system. After this the samples hit the AD9625 core. | If we look at the data path of the devices independently (see block diagram above), we can see that alignment and deskew happens at various stages. The transceivers perform deskew and alignment of bits (comma character alignment and 10B to 8B conversion), the JESD-IP then aligns individual lanes and outputs data with a fixed latency using SYSREF. The SYSREF resets the LMFC, thus the receiver knows from the time it receives the SYSREF pulse to the first received ILA data the latency of the system. After this the samples hit the AD9625 core. |
| |
| The cores receives two samples from each of the devices. Now it needs to know which samples goes first (in time) and which one follows it. That is, the samples are to be interleaved in the same order they were sampled in absolute time. Ideally being a JESD204B subclass-1 devices using SYSREF should have been sufficient to do this. The SYSREF is the "absolute" reference for all the concerned transmit and receive devices. However, for practical reasons, SYSREF is seldom used as a clock but as data and is sampled by the concerned parties at their own clock. A robust method is to identify, at the receiving device, the exact sample at which (or immediately after) the device sampled SYSREF. So the AD9625 supports a mode in which a time stamp is attached to the samples. The details of which are in the [[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf|data sheet]]. The FPGA design simply uses this time stamp and knows the exact sample at which the devices sampled SYSREF. The design implements this by aligning samples across the 16-sample data per device per clock. After which, data is written to a small FIFO with the write pointer reset by the SYSREF time stamp. A common read pointer is then used to read the samples. The FIFO supports deskewing of upto 8 samples. The ADC pack simply interleaves these samples assuming device-0 is first in order. The software need to make sure that device-0 always samples SYSREF half a clock ahead of device-1. This is done with a calibration routine. | The cores receive two samples from each of the devices. Now it needs to know which samples goes first (in time) and which one follows it. That is, the samples are to be interleaved in the same order they were sampled in absolute time. Ideally being a JESD204B subclass-1 devices using SYSREF should have been sufficient to do this. The SYSREF is the "absolute" reference for all the concerned transmit and receive devices. However, for practical reasons, SYSREF is seldom used as a clock but as data and is sampled by the concerned parties at their own clock. A robust method is to identify, at the receiving device, the exact sample at which (or immediately after) the device sampled SYSREF. So the AD9625 supports a mode in which a time stamp is attached to the samples. The details of which are in the [[http://www.analog.com/media/en/technical-documentation/data-sheets/AD9625.pdf|data sheet]]. The FPGA design simply uses this time stamp and knows the exact sample at which the devices sampled SYSREF. The design implements this by aligning samples across the 16-sample data per device per clock. After which, data is written to a small FIFO with the write pointer reset by the SYSREF time stamp. A common read pointer is then used to read the samples. The FIFO supports deskewing of up to 8 samples. The ADC pack simply interleaves these samples assuming device-0 is first in order. The software needs to make sure that device-0 always samples SYSREF half a clock ahead of device-1. This is done with a calibration routine. |
| |
| //The AD9625 supports time stamp insertion at the LSB of the sample (and is the ONLY option in certain lane configurations). This changes the devices to 11-bit converters. The HDL design does NOT support this. It supports time stamp insertion in the CS bits ONLY. The converter resolution remain as 12-bit. If you would prefer the LSB option, you need to change both HDL and software.// | //The AD9625 supports time stamp insertion at the LSB of the sample (and is the ONLY option in certain lane configurations). This changes the devices to 11-bit converters. The HDL design does NOT support this. It supports time stamp insertion in the CS bits ONLY. The converter resolution remains as 12-bit. If you would prefer the LSB option, you need to change both HDL and software.// |
| |
| |
| ==== Interleaving (SW) ==== | ==== Interleaving (SW) ==== |
| |
| The software programs both the devices and the GPIO, transceivers and IP cores in FPGA. The default transceiver setup only supports single-chip, single-link configuration. It also does not take into account that a single SYSREF controls both the devices and transceivers. The default routine is therefore modified to leave the transceivers up and running but the data path is held under reset. This is required, because the AD9625 does NOT always wait for SYSREF to start the ILA phase after CGS. The second SYSREF may reset the LMFC, but in its absence ILA phase is initiated. | The software programs both the devices and the GPIO, transceivers and IP cores in FPGA. The default transceiver setup only supports single-chip, single-link configuration. It also does not take into account that a single SYSREF controls both the devices and transceivers. The default routine is therefore modified to leave the transceivers up and running but the data path is held under reset. This is required because the AD9625 does NOT always wait for SYSREF to start the ILA phase after CGS. The second SYSREF may reset the LMFC, but in its absence, ILA phase is initiated. |
| |
| This is the section of the code where the initial setup is done. The setup and calibration of interleaving follows this. | This is the section of the code where the initial setup is done. The setup and calibration of interleaving follow this. |
| |
| <xterm> | <xterm> |
| {{ :resources:eval:user-guides:fmcadc5_ila_2_4.png?800 |FMCADC5-ILA}} | {{ :resources:eval:user-guides:fmcadc5_ila_2_4.png?800 |FMCADC5-ILA}} |
| |
| 3. The same above with values zoomed in, notice that the alternative samples are swapped, but within themselves they maintain the increasing order. | 3. The same above with values zoomed in, notice that the alternative samples are swapped, but within themselves, they maintain the increasing order. |
| |
| {{ :resources:eval:user-guides:fmcadc5_ila_2_2.png?800 |FMCADC5-ILA}} | {{ :resources:eval:user-guides:fmcadc5_ila_2_2.png?800 |FMCADC5-ILA}} |
| {{ :resources:eval:user-guides:fmcadc5_ila_3_1.png?800 |FMCADC5-ILA}} | {{ :resources:eval:user-guides:fmcadc5_ila_3_1.png?800 |FMCADC5-ILA}} |
| |
| If interleaving is in correct order, it may still appear to be out of order. This is due to the differences in the offset and gain parameters. It should be less visible when the input gradient is high but at the peaks must be clearly visible. Here is the plot with interleaving in-order. | If interleaving is in the correct order, it may still appear to be out of order. This is due to the differences in the offset and gain parameters. It should be less visible when the input gradient is high but at the peaks must be clearly visible. Here is the plot with interleaving in-order. |
| |
| 1. Interleaved signal | 1. Interleaved signal |
| |
| {{ :resources:eval:user-guides:fmcadc5_ila_5_5.png?800 |FMCADC5-ILA}} | {{ :resources:eval:user-guides:fmcadc5_ila_5_5.png?800 |FMCADC5-ILA}} |
| |
| |
| |
| ==== Modifications ==== | ==== Modifications ==== |
| |
| An alternative to software calibration is to use a calibration signal (connector J15) and let the HDL make the decision. This is in the works and I will update this section shortly. | An alternative to software calibration is to use a calibration signal (connector J15) and let the HDL make the decision. This is in the works and I will update this section shortly. |
| |
| |
| ===== Downloads (Hardware) ===== | |
| |
| ===== Downloads (HDL) ===== | ===== Downloads (HDL) ===== |
| |
| {{page>/resources/fpga/docs/hdl/downloads_insert#fmcadc5&nofooter&noeditbtn}} | {{page>/resources/fpga/docs/hdl/downloads_insert#fmcadc5&nofooter&noeditbtn}} |
| | |
| {{page>/resources/fpga/docs/hdl/downloads_insert#help_support&nofooter&noeditbtn}} | {{page>/resources/fpga/docs/hdl/downloads_insert#help_support&nofooter&noeditbtn}} |
| |
| |
| <WRAP center round download> | <WRAP center round download> |
| * AD-FMCADC5-EBZ No-OS - https://github.com/analogdevicesinc/no-OS/tree/master/ad-fmcadc5-ebz | * AD-FMCADC5-EBZ No-OS - https://github.com/analogdevicesinc/no-OS/tree/master/fmcadc5 |
| </WRAP> | </WRAP> |
| |
| ===== Downloads (Linux) ===== | |
| |
| |
| |
