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resources:eval:user-guides:ad-fmcadc4-ebz [22 Feb 2017 19:23]
larsc Canonical spelling of JESD204B
resources:eval:user-guides:ad-fmcadc4-ebz [13 Mar 2018 13:53] (current)
andrei_g 2017_r1 - Updates (remove ILA and 1.24G config)
Line 51: Line 51:
  
   - Clone [[https://​github.com/​analogdevicesinc/​no-OS|No-OS]] repository   - Clone [[https://​github.com/​analogdevicesinc/​no-OS|No-OS]] repository
-  - Checkout the '​dev' ​branch (git checkout ​dev+  - Checkout the latest release ​branch (git checkout ​branch)[[https://​github.com/​analogdevicesinc/​hdl/​releases|hdl release notes]] 
-  - Change the directory to `ad-fmcadc4-ebz/zc706`. +  - Change the directory to `fmcadc4/​zc706`. 
-  - Make the elf file by running `make HDF-FILE=<​HDL-REPO>/​projects/​fmcadc4/​zc706/​fmcadc4_zc706.sdk/​system_top.hdf`+  - Make the elf file by running ​`make` or `make HDF-FILE=<​HDL-REPO>/​projects/​fmcadc4/​zc706/​fmcadc4_zc706.sdk/​system_top.hdf` 
 +  - `make run` to download trough JTAG the hdl bitstream and software elf, this will also start the processor 
 +  - `make capture` read through the memory debugger the captured samples in RAM. Tha data will be saved in .csv files
  
-The make will build the default '​hello-world',​ but we only need the bsp and I am no fan of eclipse, hence this method. ​If you are more comfortable with the GUI, import all the files (or folders) that the make uses.+If you are more comfortable with the GUI, import all the files (or folders) that the make uses.
  
 A typical run looks like this: A typical run looks like this:
Line 81: Line 83:
 </​xterm>​ </​xterm>​
  
-The folder contains a zc706.tcl file that you can launch with xmd. You can also run it using Vivado or SDK - up to you.+For the `make run` case. You can also run it using Vivado or SDK - up to you.
  
 <​xterm>​ <​xterm>​
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]> ​xmd -tcl zc706.tcl  +[~/​github/​noos/​fmcadc4/​zc706]> ​make run
-rlwrap: warning: your $TERM is '​xterm'​ but rlwrap couldn'​t find it in the terminfo database. Expect some problems. +
-                                                                                                                                                                                                  +
-****** Xilinx Microprocessor Debugger (XMD) Engine +
-****** XMD v2015.2 (64-bit) +
-  **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 +
-    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +
- +
-Executing user script : zc706.tcl +
-Configuring Device 2 (xc7z045) with Bitstream -- hw/​system_top.bit ​                                                                                                                               +
-....................10...................20...................30....................40...................50...................60....................70...................80...................90....................Done +
-Successfully downloaded bit file. +
- +
-JTAG chain configuration +
--------------------------------------------------- +
-Device ​  ID Code        IR Length ​   Part Name +
- ​1 ​      ​4ba00477 ​          ​4 ​       arm_dap +
- ​2 ​      ​23731093 ​          ​6 ​       xc7z045 +
- +
- +
-JTAG chain configuration +
--------------------------------------------------- +
-Device ​  ID Code        IR Length ​   Part Name +
- ​1 ​      ​4ba00477 ​          ​4 ​       arm_dap +
- ​2 ​      ​23731093 ​          ​6 ​       xc7z045 +
- +
--------------------------------------------------- +
-Enabling extended memory access checks for Zynq. +
-Writes to reserved memory are not permitted and reads return 0. +
-To disable this feature, ​run "​debugconfig -memory_access_check disable"​.+
  
---------------------------------------------------+ make run 
 +xsdb  ../../../no-OS/​scripts/​xsdb.tcl ZYNQ_PS7 
 +attempting to launch hw_server
  
-CortexA9 Processor Configuration +****** Xilinx hw_server v2017.4.1 
-------------------------------------- +  **** Build date : Jan 30 2018-15:​42:​25 
-Version.............................0x00000003 +    ** Copyright 1986-2017 Xilinx, IncAll Rights Reserved.
-User ID.............................0x00000000 +
-No of PC Breakpoints................6 +
-No of Addr/Data Watchpoints.........4+
  
-Connected ​to "​arm"​ target. id = 64 +INFO: hw_server application started 
-Starting GDB server for "​arm"​ target (id = 64) at TCP port no 1234 +INFO: Use Ctrl-C ​to exit hw_server application
-Processor stopped+
  
-Processor Reset .... DONE                                                                                                                                                                         +INFOTo connect to this hw_server instance use urlTCP:127.0.0.1:3121
-Downloading Program -- zc706.elf +
-        section, .text0x00100000-0x0010656b +
-        section, .init0x0010656c-0x00106583 +
-        section, .fini0x00106584-0x0010659b +
-        section, ​.rodata: 0x0010659c-0x00106927 +
-        section, ​.data: 0x00106928-0x00106e9b +
-        section, ​.eh_frame0x00106e9c-0x00106e9f +
-        section, .mmu_tbl: 0x00108000-0x0010bfff +
-        section, .ARM.exidx: 0x0010c000-0x0010c007 +
-        section, .init_array:​ 0x0010c008-0x0010c00f +
-        section, .fini_array:​ 0x0010c010-0x0010c013 +
-        section, .bss: 0x0010c014-0x0010c0a7 +
-        section, .heap: 0x0010c0a8-0x0010e0af +
-        section, .stack: 0x0010e0b0-0x001118af +
-Download Progress..10.20.30.40.50.60.70.80.90.Done +
-Setting PC with Program Start Address 0x00100000 +
-Processor started. Type "​stop"​ to stop processor+
  
-RUNNING> Disconnected from Target 64+100%    6MB   ​1.7MB/​s ​ 00:03 
 +Downloading Program -- ~/​github/​noos/​fmcadc4/​zc706/​sw/​Release/​sw.elf 
 +        section, .text: 0x00100000 - 0x00113487 
 +        section, .init: 0x00113488 - 0x0011349f 
 +        section, .fini: 0x001134a0 - 0x001134b7 
 +        section, .rodata: 0x001134b8 - 0x00114387 
 +        section, .data: 0x00114388 - 0x00114de3 
 +        section, .eh_frame: 0x00114de4 - 0x00114de7 
 +        section, .mmu_tbl: 0x00118000 - 0x0011bfff 
 +        section, .ARM.exidx: 0x0011c000 - 0x0011c007 
 +        section, .init_array:​ 0x0011c008 - 0x0011c00b 
 +        section, .fini_array:​ 0x0011c00c - 0x0011c00f 
 +        section, .bss: 0x0011c010 - 0x0011c373 
 +        section, .heap: 0x0011c374 - 0x0011e37f 
 +        section, .stack: 0x0011e380 - 0x00121b7f 
 +100%    0MB   ​0.6MB/​s ​ 00:00 
 +Setting PC to Program Start Address 0x00100000 
 +Successfully downloaded ~/​github/​noos/​fmcadc4/​zc706/​sw/​Release/​sw.elf
  
-Disconnected from Target 352 
 </​xterm>​ </​xterm>​
  
Line 155: Line 125:
  
 <​xterm>​ <​xterm>​
-AD9528 successfully initialized. +QPLL ENABLE 
-AD9680 PLL is locked. +Rx link is enabled 
-AD9680 successfully initialized. +Measured Link Clock: 250 MHz 
-AD9680 PLL is locked. +Link status: DATA 
-AD9680 successfully initialized. +SYSREF captured: Yes 
-JESD204B successfully ​initialized+adc_setup adc core initialized (1000 MHz). 
-ADC Core Initialized ​(1000 MHz). +adc_setup adc core initialized ​(1000 MHz). 
-ADC Core Initialized ​(1000 MHz). +RX capture ​done.
-Initialization done. +
- +
-Capture ​done.+
 </​xterm>​ </​xterm>​
- 
 A brief background information on what is happening. Let's look at the No-OS main function. A brief background information on what is happening. Let's look at the No-OS main function.
 First, it configures and sets the GPIO based on the board. First, it configures and sets the GPIO based on the board.
  
-<xterm+<code c
- adc4_gpio_ctl(GPIO_DEVICE_ID); +  ​ad_gpio_set(GPIO_AD9528_STATUS,​ 0x0); 
-</xterm>+ ad_gpio_set(GPIO_AD9528_RSTN,​ 0x0); // reset 
 + ad_gpio_set(GPIO_AD9528_RSTN,​ 0x1); // bring out of reset 
 +</code>
  
 The clock chip is programmed to output the desired clocks and sys-ref signals. The default setting is 1GHz for the AD9680 and 500MHz for the FPGA. The clock chip is programmed to output the desired clocks and sys-ref signals. The default setting is 1GHz for the AD9680 and 500MHz for the FPGA.
  
 <​xterm>​ <​xterm>​
- ad9528_setup(SPI_DEVICE_ID0, ad9528_pdata_lpc);+ ad9528_setup(&​ad9528_spi_device&​ad9528_param);
 </​xterm>​ </​xterm>​
  
Line 184: Line 152:
  
 <​xterm>​ <​xterm>​
-  jesd204b_gt_initialize(FMCADC4_GT_BASEADDR,​ 8);+  xcvr_setup(&​ad9680_xcvr);
 </​xterm>​ </​xterm>​
  
Line 190: Line 158:
  
 <​xterm>​ <​xterm>​
- ad9680_setup(SPI_DEVICE_ID1); + ad9680_setup(&​ad9680_0_spi_devicead9680_0_param); 
- ad9680_setup(SPI_DEVICE_ID2);+ ad9680_setup(&​ad9680_1_spi_devicead9680_1_param);
 </​xterm>​ </​xterm>​
  
-The design uses Xilinx's JESD IP- it needs to be programmed to match the device settings (frame count, byte count, scrambling and such).+The design uses ADI's JESD IP- it needs to be programmed to match the device settings (frame count, byte count, scrambling and such).
  
 <​xterm>​ <​xterm>​
-  jesd204b_setup(AD9680_JESD_BASEADDR,​ jesd204b_st);+  jesd_setup(ad9680_jesd);
 </​xterm>​ </​xterm>​
  
Line 203: Line 171:
  
 <​xterm>​ <​xterm>​
- ​ jesd204b_gt_setup(ad9680_gt_link);+  axi_jesd204_rx_status_read(ad9680_jesd);
 </​xterm>​ </​xterm>​
  
Line 209: Line 177:
  
 <​xterm>​ <​xterm>​
- adc_setup(ad9680_0, 2); + adc_setup(ad9680_0_core);
- adc_setup(ad9680_1,​ 2);+
 </​xterm>​ </​xterm>​
  
Line 218: Line 185:
  
 <​xterm>​ <​xterm>​
- ad9680_spi_write(1AD9680_REG_DEVICE_INDEX,​ 0x3); + ad9680_test(&​ad9680_0_spi_deviceAD9680_TEST_PN9);
- ​ ad9680_spi_write(1,​ AD9680_REG_ADC_TEST_MODE,​ 0x05); +
- ​ ad9680_spi_write(1,​ AD9680_REG_OUTPUT_MODE,​ 0); +
- ad9680_spi_write(2,​ AD9680_REG_DEVICE_INDEX,​ 0x3); +
- ad9680_spi_write(2,​ AD9680_REG_ADC_TEST_MODE,​ 0x05); +
- ad9680_spi_write(2,​ AD9680_REG_OUTPUT_MODE,​ 0);+
 </​xterm>​ </​xterm>​
  
Line 229: Line 191:
  
 <​xterm>​ <​xterm>​
- adc_pn_mon(ad9680_02, 1); + adc_pn_mon(ad9680_0_coreADC_PN9)
- adc_pn_mon(ad9680_1,​ 2, 1);+
 </​xterm>​ </​xterm>​
  
-If you don't see any other messages in the UART other than the ones mentioned above- all is well. You can open up Vivado and see things in ILA also.+If you don't see any other messages in the UART other than the ones mentioned above- all is well.
  
-Let's see now how we can change the sampling rate to 1.24 GHz. The AD9680 maximum sampling rate is 1.25GHz. However the board uses a 80MHz crystal as the reference clock to AD9528. Unless you change it, this limits the maximum clock output on the banks to 1.24GHz. Also note that the Kintex 7 SOC on ZC706 is a -2 device. The maximum lane rate is limited to 10Gbps. However, it should be possible to over clock the transceiver (but do so at your own risk). Officially, you must get a -3 device to run the link at 12.4Gbps. +Here is the ILA plot screen capture  
- +<​note>​We ​are not supporting ​the ILA in the reference designs since the hdl_2016_r1 release</note>
-Going back to our program. +
- +
-<​xterm>​ +
-#ifdef MODE_1_24G +
- ad9528_pdata_lpc.pll2_ndiv_a_cnt = 1; +
- ad9528_pdata_lpc.pll2_ndiv_b_cnt = 23; +
- ad9528_pdata_lpc.pll2_n2_div = 31; +
- ad9528_pdata_lpc.pll2_vco_diff_m1 = 3; +
-#endif +
-</​xterm>​ +
- +
-Let's define that macro somewhere on that file. +
- +
-<​xterm>​ +
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]>​ gitdiff.pl ../​ad_fmcadc4_ebz.c  +
-71a72 +
-> #define MODE_1_24G +
-</​xterm>​ +
- +
-And re-run the make. +
- +
-<​xterm>​ +
-[~/​github/​noos/​ad-fmcadc4-ebz/​zc706]>​ make HDF-FILE=~/​github/​hdl/​projects/​fmcadc4/​zc706/​fmcadc4_zc706.sdk/​system_top.hdf  +
-arm-xilinx-eabi-gcc -DXILINX -Ibsp/​ps7_cortexa9_0/​include -I.. -I../​../​common_drivers/​adc_core -I../​../​common_drivers/​jesd204b_gt -I../​../​common_drivers/​jesd204b_v51 -I../​../​common_drivers/​xilinx_platform_drivers -I../​../​drivers/​ad9528 -I../​../​drivers/​ad9680 -Os -ffunction-sections -fdata-sections -o zc706.elf sw/​src/​platform.c ../​ad_fmcadc4_ebz.c ../​../​common_drivers/​adc_core/​adc_core.c ../​../​common_drivers/​jesd204b_gt/​jesd204b_gt.c ../​../​common_drivers/​jesd204b_v51/​jesd204b_v51.c ../​../​common_drivers/​xilinx_platform_drivers/​platform_drivers.c ../​../​drivers/​ad9528/​ad9528.c ../​../​drivers/​ad9680/​ad9680.c -Lbsp/​ps7_cortexa9_0/​lib/​ -Tsw/​src/​lscript.ld -Wl,​--start-group,​-lxil,​-lgcc,​-lc,​--end-group +
-</​xterm>​ +
- +
-The UART should now show this. +
- +
-<​xterm>​ +
-AD9528 successfully initialized. +
-AD9680 PLL is locked. +
-AD9680 successfully initialized. +
-AD9680 PLL is locked. +
-AD9680 successfully initialized. +
-JESD204B successfully initialized. +
-ADC Core Initialized (1240 MHz). +
-ADC Core Initialized (1240 MHz). +
-Initialization done. +
- +
-Capture done. +
-</​xterm>​ +
- +
-The clocks reported by the core is 1240MHz instead of the previous 1000MHz. There are no error messages and PRBS locks. This is all there is to it. There is no need for HDL modifications. However, if you ran into trouble here are a couple of things to try. +
- +
-  * If you have ran this back to back- try running 1.24GHz option from power up. +
-  * Modify the HDL to use a -3 device and change the constraints to run at 12.40Gbps +
-  * Upgrade the device on board to a -3 device. +
- +
-Here is the UART window ​screen capture. +
- +
-{{:​resources:​eval:​user-guides:​fmcadc4_uart.png?​400|FMCADC4-UART}} +
- +
-The application leaves the device in a ramp pattern, and if you are looking at the data using ILA should see it. If you would like to switch it to the analog input, do the following. In this case I am changing only the fourth channel (SMA - J301D). +
- +
-<​xterm>​ +
- ad9680_spi_write(1,​ AD9680_REG_DEVICE_INDEX,​ 0x3); +
- ad9680_spi_write(1,​ AD9680_REG_ADC_TEST_MODE,​ 0x0F); +
- ad9680_spi_write(1,​ AD9680_REG_OUTPUT_MODE,​ 0x1); +
- +
- ad9680_spi_write(2,​ AD9680_REG_DEVICE_INDEX,​ 0x3); +
- ad9680_spi_write(2,​ AD9680_REG_ADC_TEST_MODE,​ 0x0F); +
- ad9680_spi_write(2,​ AD9680_REG_OUTPUT_MODE,​ 0x1); +
- +
- ad9680_spi_write(2,​ AD9680_REG_DEVICE_INDEX,​ 0x2); +
- ad9680_spi_write(2,​ AD9680_REG_ADC_TEST_MODE,​ 0x00); +
- ad9680_spi_write(2,​ AD9680_REG_OUTPUT_MODE,​ 0x1); +
-        adc_write(ad9680_1,​ ADC_REG_CHAN_CNTRL(1),​ 0x51); +
-</xterm> +
- +
-Here is the ILA plot screen capture.+
  
 {{:​resources:​eval:​user-guides:​fmcadc4_ila.png?​500|FMCADC4-ILA}} {{:​resources:​eval:​user-guides:​fmcadc4_ila.png?​500|FMCADC4-ILA}}
- 
- 
- 
  
 ===== Downloads (Hardware) ===== ===== Downloads (Hardware) =====
resources/eval/user-guides/ad-fmcadc4-ebz.txt · Last modified: 13 Mar 2018 13:53 by andrei_g