The EVAL-ADAQ8092-FMCZ evaluates the ADAQ8092, a 14-bit, 105MSPS , high-speed dual-channel data acquisition uModule solution. This device uses the System-in-Package (SiP) that integrates three common signal processing and conditioning blocks.
This EVAL-ADAQ8092-FMCZ board does not need an external power supply to operate and requires a very small jitter in the clock source. We recommend to use the DC1075B to improve the clock signal source. For full details on the ADAQ8092, see the ADAQ8092 data sheet, which must be consulted in conjunction with this user guide when using the EVAL-ADAQ8092-FMCZ.
The installer can also be run from within ACE by clicking the link found in the 'IIIO Resources' section found in the Help » Application Resources section.
If there is a need to re-image or create a new SD card, instructions are available here: ADI Kuiper Linux with support for ACE Evaluation.
To avoid potential damage, ensure the VADJ SELECT jumper is set to the correct voltage for the Product Evaluation Board.
There may be additional steps and hardware required for a given Product Evaluation Board, for example, function generators connections and setup. This information may be included with the eval kit or in the User guide for the corresponding Product Evaluation Boards page that can be found by searching Product Evaluation Boards and Kits.
Figure 2 shows the EVAL-ADAQ8092-FMCZ block diagram. The ADAQ8092 µModule that is soldered to the EVAL-ADAQ8092-FMC does not require external supply to power-up the board. It uses the +12V supply source from the data capture board such as Zedboard and activates the LDO’s to provide the 3.3V and 1.8V needed of the board.
Figure 3. Analog Input Circuitry of EVAL-ADAQ8092-FMCZ
The EVAL-ADAQ8092-FMCZ provides the user to either use a single-ended or differential source. For the single-ended source, user can either use the balun so that the part will still be driven differentially or bypass it to drive the part single-endedly. Installation of 0 ohm resistor is used to configure the input of the analog input circuitry.
Table 1. Factory Default Settings (Single-ended input driven)
|1||JP1||Pin 2 to Pin 3|
|JP3||Pin 2 to Pin 1|
|JP4||Pin 2 to Pin 3|
|2||JP2||Pin 2 to Pin 3|
|JP5||Pin 2 to Pin 1|
|JP6||Pin 2 to Pin 3|
Note: Without changing other resistor values of the board, then this board is ready for a single ended source that drives the part single-endedly but if the user uses a differential source then install a 49.9ohm resistor at R1 and R3 for Channel 1 and Channel 2, respectively. This is to properly balance the inputs when driven differentially. Refer to Figure 6 and Figure 7 for schematic.
Table 2. Differentially driven using the balun
|1||JP1||Pin 2 to Pin 1|
|JP3||Pin 2 to Pin 3|
|JP4||Pin 2 to Pin 1|
|2||JP2||Pin 2 to Pin 1|
|JP5||Pin 2 to Pin 3|
|JP6||Pin 2 to Pin 1|
Note: When using this configuration, resistor value should also be changed to properly balance the impedance and make the gain still equal to approximately equal to 5. For channel 1; R8 and R9 should be 200 ohms and R14 and R16 is 18.2 ohms. For channel 2; R10 and R11 should be 200 ohms and R15 and R17 is 18.2 ohms. Refer to Figure 6 and Figure 7 for schematic.
Figure 4. Encode Circuitry of EVAL-ADAQ8092-FMCZ
The user can either use a single-ended encode mode or a differential encode mode. The default configuration of the EVAL-ADAQ8092-FMCZ uses the single-ended encode mode that requires a CMOS level. Also, the board provides an option to install an oscillator (Y1) and use it as a built-in clock for a single-ended encode mode.
When using a sinusoidal, PECL or LVDS signal then it is suggested to use the differential encode mode.
Figure 5. Power Circuitry of EVAL-ADAQ8092-FMCZ
The EVAL-ADAQ8092-FMC uses the +12V supply from the data capture board such as Zed board at C35 of the FMC (FPGA Mezzanine Card) connector pin configuration. This +12V supply goes to a reverse input protection by the used of LTC4359 (U2) and then proceed with a step down regulator, LTM8074 (U4). The output of the LTM8074 which is configured to have 5V output will then supply the LTC1673-1.8 (U3) and LTC1763-3.3 (VR1). The LTC1763-1.8 will be VDD and OVDD supplies, while the LTC1763-3.3 will be the VCC supply.
External supplies can also be used when some of the built-in power circuitry is failing. Re-work of the board is needed to achieve this.
Figure 6. Schematic of EVAL-ADAQ8092-FMCZ (page 1)
Figure 7. Schematic of EVAL-ADAQ8092-FMCZ (page 2)
Figure 8 illustrates the evaluation system components. To use the system, here's the following steps:
The ZedBoard, which is the system controller board, enables the configuration of the ADC and capture of data from the evaluation board by the PC via USB (or Ethernet). The ADAQ8092 support a multi-lane serial port interface (SPI) for each data converter channel. The SPI interface for each channel is connected to the ZedBoard via the FMC connector (P1). The ZedBoard™ functions as the communication link between the PC and connected evaluation board. It buffers samples captured from the evaluation board in its DDR3 memory. The ZedBoard board requires power from a 12 volt wall adapter (included with the ZedBoard). It hosts a Xilinx® ZYNQ® 7020 SoC, which contains two ARM® Cortex-A9 Processors and a Series-7 FPGA with 85k Programmable Logic cells. A Linux OS runs on the host processor system. It communicates with the PC through either a USB 2.0 high speed port or a 10/100/1000 Ethernet port. The default software configuration uses USB.
To start the ACE evaluation software, here are the following steps:
Figure 9. Start Window
Figure 10. ADAQ8092 Board Window
Figure 11. ADAQ8092 (Chip) Window
Here in the ANALYSIS window, there are three (3) panes, the CAPTURE pane, ANALYSIS pane, and RESULTS pane.
Figure 12. Waveform view
Figure 13. FFT view
Figure 14. Average FFT view
Figure 15. INL view
Figure 16. DNL view