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ADAQ23876/ADAQ23878 User Guide (Evaluating Using ZedBoard)


  • Evaluation board for ADAQ23876 and ADAQ23878 (16-/18-bit 15MSPS) μModule Data Acquisition Solutions
  • Versatile analog signal conditioning circuitry
  • On-board reference, LDO, and power supply circuits
  • PC software for control and data analysis of time and frequency domain

Evaluation Requirements


  • EVAL-ADAQ23876 or EVAL-ADAQ23878 evaluation board
  • Zedboard (AES-Z7EV-7Z020-G)
  • 12V power supply
  • Host PC running on Windows 10 or higher
  • SD Card (16GB or larger)
  • LAN Cable
  • SMA Cable
  • XLR to SMA adapter cable
  • Audio Analyzer (Audio Precision© APX525) or other input source


General Description

The EVAL-ADAQ23876 and EVAL-ADAQ23878 evaluation boards enable a simplified evaluation of the performance of the ADAQ23876 and EVAL-ADAQ23878 15MSPS, 16-/18-bit, High Speed, Precision μModule Data Acquisition Solutions.

The ADAQ23876 and ADAQ23878 μModules incorporates various signal processing and conditioning blocks into devices that include a low noise, fully differential analog-to-digital converter (ADC) driver, a stable high resolution reference buffer with 16-/18-bit, 15MSPS successive approximation register (SAR) ADCs, and the critical passive components necessary for optimum performance.

To learn more about these μModules, refer to the datasheet of ADAQ23876 and ADAQ23878. This user guide should be used with ADAQ23876 and ADAQ23878's datasheet to achieve the best performance during evaluation.

Figure 1: EVAL-ADAQ23876FMCZ / EVAL-ADAQ23878FMZ Evaluation Board

Getting Started

The following section contains the evaluation instructions for EVAL-ADAQ23876FMCZ/EVAL-ADAQ23878FMCZ evaluation board using IIO Oscilloscope.

Setting Up the Evaluation Board

The evaluation board consists of one μModule (U1, ADAQ23878 or ADAQ23876), a choice of a 4.096V reference (U5, LTC6655) or 2.048V reference (U3, ADR4520), on-board power supplies to drive the necessary supply rails using the LTM8049 (U6), the ADP7118 (U4), the ADP7183 (U7), the LT3023 (U8), and an 800 MHz clock distribution IC (U13). The user also has an option to use the A2 and A3 amplifiers, such as the ADA4899-1, when evaluating the ADAQ23876 or ADAQ23878.

Power Supplies

The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ can be powered from an external 3.3 V supply applied using the JP9 solder link if desired (see Table 2). The positive rails of the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ, 7 V (+VS), 5 V (VDD), and 2.5 V (VIO), are generated from a combination of the power µModule, LTM8049 (U6), ADP7118 (U4), and a dual output low dropout (LDO) regulator, LT3023 (U8). The negative rail of the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ, −2.0 V (−VS), is generated by a combination of the power µModule, LTM8049 (U6), and ADP7183 (U7). Each supply rail has necessary decoupling capacitors placed close to the device. A single ground plane is used on the board to minimize the effect of high frequency noise interference.

Table 1: On-Board Power Supplies

Analog Inputs

The Subminiature Version A (SMA) connectors (VIN+ and VIN−) on the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ are used to provide analog inputs from a low noise, audio precision signal source (such as the SYS-2700 or the SYS-x555 series). There are two options available to feed analog inputs directly to the ADA4899-1 and ADAQ23876 or ADAQ23878.

The optional amplifiers, ADA4899-1 (A2, A3), can be set up in a unity-gain configuration driving the ADAQ23876 or ADAQ23878. In a default configuration of the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ, an input signal via VIN+ and VIN can be fed directly to the ADAQ23876 or ADAQ23878, respectively, by bypassing A2 and A3.

The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ are factory configured to provide the appropriate input signal type, single-ended or fully differential, and different gain/attenuation or input range scaling. Table 2 lists the necessary jumper positions and link options for different configurations. The default board configuration presents a 4.096 V on the REFBUF pin and a buffered 2.048V (midscale) of the fully differential ADC driver amplifier (FDA)'s VCMO pin of the ADAQ23876 and ADAQ23878.

For low input frequency testing below 100 kHz, it is recommended to use a low noise, audio precision signal source (such as the SYS-2700 series) with the outputs set to balanced floating. A different precision signal source can be used alternatively with additional band-pass filtering. The filter bandwidth depends on input bandwidth of interest.

Multiple link options must be set correctly for the inappropriate operating setup before applying the power and signal to the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ. Refer to the link below for the link options for this evaluation boards.

Table 2: Link Options for the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ

Evaluation Board Connector Configuration

The functional descriptions for all the connectors used on the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ are listed in Table 4 and Table 5. There are several test points and single in line (SIL) headers on the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ. These test points provide easy access to on-board signals for troubleshooting and evaluation purposes. Table 3 details the different gain positions for the links of the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ.

Click here to see the different Connector Configurations

Table 3: Gain Input Configuration

Table 4: On-Board Connectors

Table 5: 160-Pin FMC Connector (P5) Details

1 User defined signals with a P suffix can be used as the positive pin of the differential pair. User defined signals with an N suffix can be used as the negative pin of the differential pair. For further information, see the VITA 57 specification.

2 User defined signals with a CC suffix are the preferred signal lines on which to transmit clock signals from the controller board to the daughter board. These signal lines are connected to global clock lines on the FPGA, but they can also be used to carry any other user defined signal. For further information, see the VITA 57 specification.

Loading Image in the SD Card

To properly evaluate the EVAL-ADAQ23876/EVAL-ADAQ23878, you need to ensure that the ADI Kuiper Linux is properly flashed on the SD card. Complete instructions on how to properly download, write and configure the image can be accessed at Kuiper Images. Make sure to comply with the directions for preparing the image for ADAQ23876/ADAQ23878.

SD Card Preparation

Follow these steps to prepare the SD Card,

Ensure that the SD card is loaded with the latest version of the ADI Kuiper Image.
  1. Download the ADI Kuiper Image

    The Analog Devices Kuiper Linux image is an open-source, embedded Linux operating system based on Raspberry Pi OS. It incorporates Linux device drivers for ADI products as well as tools and other software products designed and created for ease of use.

    • Use the image for CN0577.
    • Access to the embedded system can be through ​a remote PC connected ​either via LAN cable or Wi-Fi.
Ensure that the SD Card is configured for the correct FPGA project. You may refer to the steps identified in ADI Kuiper Images to properly configure the image based on the correct FPGA project. Key files that need to be saved in the root folder are:
  2. devicetree.dtb
  3. uImage found in the zynq-common folder

Hardware Connection

Figure 8: Signal Chain Connection

Follow these steps to setup the complete system using Audio Precision Audio Analyzer as input source.

  1. Download and install the IIO Oscilloscope application that is suitable for the host PC.
  2. Flash the Analog Devices Kuiper Linux image on the SD card.
  3. Properly configure the SD card for EVAL-ADAQ23876/EVAL-ADAQ23878.
  4. Insert the SD card into the ZedBoard.
  5. Attach the EVAL-ADAQ23876/EVAL-ADAQ23878 to the ZedBoard through the FMC pin connector.
  6. Power up the ZedBoard using the 12V cable.
  7. Connect the EVAL-ADAQ23876/EVAL-ADAQ23878 to the Audio Precision Audio Analyzer using the XLR to SMA adapter cable.
  8. Connect the Audio Precision Audio Analyzer USB cable to the PC.

Once all steps are done, the IIO Oscilloscope software should run smoothly.

Main Window

Each plugin (or tab) can be detached from the main window simply by clicking on the button placed on the right side of the name of the plugin. Close the detached window to attach the plugin back to the main window. The Main Window is designed to display a configuration panel (plugin) for each device recognized by the system. Additional plugins will be loaded for device debugging and monitoring purposes such as Debug Tab/Plugin and DMM Tab/Plugin.

Figure 9: Main Window

Debug Tab/Plugin

Debug Plugin is a tool for device debugging. Since “normal” users should not be doing this, features on this tab may not work unless you have started the osc application as root.

  1. Device Selection: Sets the active device. Once a device is selected any other information displayed in the plugin is related to this particular device.
  2. IIO Device Attributes: Allows Read/Write operation for the attributes of a device.
  3. Register: Provides low level access to the registers of the device.
    • a. Enable AutoRead: When enabled it allows the register to be read automatically as the register address changes.
    • b. Address: The address of the register
    • c. Value: The value of the register at the given address.

Figure 10: Debug Tab/Plugin

DMM Tab/Plugin

DMM Plugin: The Digital Multimeter continuously displays device specific data once the start button is activated.

  1. Device tab: Displays the list of all available devices.
  2. Active channels tab: Displays the list of channels that belong to the enabled devices. All channels can be enabled simultaneously by using the All Channels button.
  3. Right side tab: Displays data readings of the enabled channels in Active channels tab.

Figure 11: DMM Tab/Plugin

Capture Window

The Capture Window is where device data is displayed.

  • Menu (Along the top of the capture/plot window)
    • File
      • Save As: Saves data to file.
      • Quit: Close the capture/plot window
    • Edit
      • Plot Title: Change the name of the window.
    • View
      • Show Settings: show/hide all settings in the left panel and allow the plot to fill the entire window.
      • Full Screen: Will make the window full screen.
  • Plot Options/Icons (along the top of the window)
    • Capture/Stop: Starts or stops the data capture
    • Zoom In: Zooms in on a region of the plot
    • Zoom Out: Zooms out from a region of the plot
    • AutoZoom: Zooms automatically for the signal to fit the screen
    • Save As: Saves data to file
    • FullScreen: Enters/leaves fullscreen
    • Auto scale: When enabled the visible area will automatically be re-scaled to fit the entire plot
    • Show grid: Show or hides the grid in the plot window
    • Y Max: Adjusts the upper limit of the vertical axis when Auto scale is disabled
    • Y Min: Adjusts the lower limit of the vertical axis when Auto scale is disabled
    • New Plot: Creates a new plot of the same type.
  • Plot Type: Time Domain -Plots the signal in the time domain. Displays the raw samples.
    1. Sample Count: Selects the number of samples for time domain, constellation and cross-correlation plotting
    2. Graph Type: Selects the type of all graphs: lines or dots.

Figure 12: Time Domain Plot

  • Plot Type: Frequency Domain -Plots the signal in the frequency domain. Performs a FFT on the signal and displays it.
    1. FFT size: Selects the size of the FFT for frequency domain plotting
    2. Window: Selects the FFT Window. Each window function has its own characteristics and suitability for different applications. Click here to know more about selecting the most appropriate window function.
    3. FFT Average: Selects the average weight to be applied to the FFT samples.
    4. PWR Offset: Selects the offset of the FFT graph.

Figure 13: Frequency Domain Plot

  • Plot Type: Constellation -Plots the signal as a constellation plot. The I-channel will be plotted on the x-axis and the Q-channel on the y-axis.
    1. Sample Count: Selects the number of samples for time domain, constellation and cross-correlation plotting
    2. Graph Type: Selects the type of all graphs: lines or dots.
  • Plot Type: Cross Correlation -Plots the signal as a cross-correlation plot.
    1. Sample Count: Selects the number of samples for time domain, constellation and cross-correlation plotting
    2. Graph Type: Selects the type of all graphs: lines or dots.
Several waveforms are provided for demonstration purposes, which can be loaded into different devices. However, these are generally not meant for transceiver characterization or demodulation. If you want to do such tasks, it is recommended to create your own waveform using other tools such as MATLAB
  • Info
    • Markers: Displays marker measurements.
    • Devices: Displays Device info (sample rate)
  • Activating Markers

Markers are used for plot data measurement when looking in the frequency domain or during cross correlation. To activate the markers, right click on the plot and select from the marker menu the type of marker you want to enable. Ensure that the capture process is running and the appropriate domain is selected in order to enable the markers properly. The following types of markers are available:

  • FFT domain (1 channel enabled): Peak, Fixed and Single Tone markers
  • FFT domain (2 channel enabled): Peak, Fixed, Single Tone and Image markers
  • Constellation: Peak Marker

The enabling of a marker will display a set of 5 markers by default. You can add more markers by selecting Add Marker from the marker menu and remove some by selecting Remove Marker.

Saving Captured Data

Once a data is captured, it can be saved using on of the following formats:

  • Agilent VSA
  • .csv
  • .mat
  • .png

Figure 14: Save As Window

Evaluating the EVAL-ADAQ23876 FMCZ / EVAL-ADAQ23878FMCZ using IIO Oscilloscope

Make sure to download/update to the latest version of IIO-Oscilloscope.

  1. Ensure that you are using the latest version of IIO Oscilloscope.
  2. Select the Refresh button to display the available IIO devices.

    Figure 15: Refreshing the IIO Oscilloscope Connection

  3. Once ltc2387 appears, select Connect.

    Figure 16: Connecting the IIO Oscilloscope

IIO Oscilloscope Capture Window

Waveform Plot

Figure 17: Time Domain Waveform Plot

FFT Plot

Figure 18: FFT Plot

To Start

To obtain the FFT plot, follow the ff steps:

  1. Select “Frequency Domain” for the plot type

    Figure 19: Selecting the Plot Type

  2. Designate your preferred number of samples under FFT size

    Figrue 20: Setting the No. of Samples

  3. Specify the window type to “Blackmann-Harris”.

    Figure 21: Selecting the Window Type

  4. Press run to view the result.

    Figure 22: View the result

Board Layout Guidelines

The printed circuit board (PCB) layout is critical for preserving signal integrity and achieving the expected performance from the ADAQ23876 and ADAQ23878. A multilayer board with an internal, clean ground plane in the first layer beneath the ADAQ23876 and ADAQ23878 is recommended. Care must be taken with the placement of individual components and routing of various signals on the board. It is highly recommended to route input and output signals symmetrically. Solder the ground pins of the ADAQ23876 or ADAQ23878 directly to the ground plane of the PCB using multiple vias. Remove the ground and power planes under the analog input/output and digital input/output (including F1 and F2) pins of the ADAQ23876 or ADAQ23878 to avoid undesired parasitic capacitance. Any undesired parasitic capacitance can impact the distortion and linearity performance of the ADAQ23876 and ADAQ23878.

The pinout of the ADAQ23876 and ADAQ23878 eases the layout and allows its analog signals on the left side and its digital signals on the right side. The sensitive analog and digital sections must be separated on the PCB while keeping the power supply circuitry away from the analog signal path. Fast switching signals, such as CNV± or CLK±, and the DA± and DB± digital outputs must not run near or cross over analog signal paths to prevent noise coupling to the ADAQ23876 and ADAQ23878.

Good quality ceramic bypass capacitors of at least 2.2 µF (0402,X5R) must be placed at the output of LDO regulators generating the µModule supply rails (VDD, VIO, VS+, and VS-) to GND to minimize electromagnetic interference (EMI) susceptibility and to reduce the effect of glitches on the power supply lines. All the other required bypass capacitors are laid out within the ADAQ23876 and ADAQ23878, saving extra board space and cost. When the external decoupling capacitors on REFIN, VDD, and VIO pins near the µModule are removed, there is no significant performance impact.

Mechanical Stress

The mechanical stress of mounting a device to a board can cause subtle changes to the SNR and internal voltage reference. The best soldering method is to use IR reflow or convection soldering with a controlled temperature profile. Hand soldering with a heat gun or a soldering iron is not recommended.

Board Schematic and PCB Layout

EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ Design and Integration Files

  • Schematics
  • PCB Layout
  • Bill of Materials
  • Allegro Project

End of Document

resources/eval/user-guide/adaq23876/adaq23878.1708567837.txt.gz · Last modified: 22 Feb 2024 03:10 by Regine Garcia