This describes the hardware design of the EVAL-SDP-CH1Z board.
This green LED indicates that the three power supplies supplying power to the FMC connector (12P0V, 3P3V and VADJ) are turned on.
This green LED indicates that the SDP-H1 Blackfin processor is powered. This is not an indication of USB connectivity between the SDP-H1 and the PC.
This green LED indicates whether or not the FPGA has been configured. When it is turned off the FPGA is unconfigured. When it is turned on the FPGA is configured. During repeated FPGA configuring, the LED will momentarily turn off until the configuration process has completed.
These red (LED0), orange (LED1) and green (LED2) LEDs are connected to the FPGA and can be used by the user for whatever purpose they see fit.
The orange status LED is an LED used as a diagnostic tool for evaluation application developers. When there are two or more identical SDP controller board and daughter board combin-ations connected to the PC simultaneously, the status LED flashes during the connect routine to help the user identify which board they will communicate with.
This green LED indicates that the power supplies supplying power to the FPGA, DDR2, SRAM and Blackfin are turned on.
The SDP-H1 board has a 120-pin SDP connector and a Low Pin Count (LPC) female FMC connector.
Through this Hirose FX8-120P-SV1(91), 120 pin header, connector, the peripheral communication interfaces of ADSP-BF527 Blackfin processor are exposed. The exposed peripherals are:
Also, included on the connector specification are input and output power pins, ground pins, and pins reserved for future use.
For further details on the peripheral interfaces, including timing diagrams, see the ADSP-BF52x Blackfin Processor Hardware Reference
The connector pin assignments for the Connector A has been defined independently of the any internal pin sharing that occurs on the Blackfin processor. The below table lists the connector pins and identifies the functionality assigned to each connector pin for Connector A.
Pin No. | Pin Name | Description |
---|---|---|
1 | VIN | Power to SDP-B board. Requires 200mA @ 4 – 7 Volts. |
2 | NC | No Connect. Leave this pin unconnected. Do not ground. |
3 | GND | Connect to ground plane of board. |
4 | GND | Connect to ground plane of board. |
5 | USB_VBUS | Connected directly to the USB +5v Supply. |
6 | GND | Connect to ground plane of board. |
7 | PAR_D23 | Parallel Data Bus Bit 23.(No connect.) 1 |
8 | PAR_D21 | Parallel Data Bus Bit 21.(No connect.) 1 |
9 | PAR_D19 | Parallel Data Bus Bit 19.(No connect.) 1 |
10 | PAR_D17 | Parallel Data Bus Bit 17.(No connect.) 1 |
11 | GND | Connect to ground plane of board. |
12 | PAR_D14 | Parallel Data Bus Bit 14. |
13 | PAR_D13 | Parallel Data Bus Bit 13. |
14 | PAR_D11 | Parallel Data Bus Bit 11. |
15 | PAR_D9 | Parallel Data Bus Bit 9. |
16 | PAR_D7 | Parallel Data Bus Bit 7. |
17 | GND | Connect to ground plane of board. |
18 | PAR_D5 | Parallel Data Bus Bit 5. |
19 | PAR_D3 | Parallel Data Bus Bit 3. |
20 | PAR_D1 | Parallel Data Bus Bit 1. |
21 | PAR_RD | Low Enable. Asynchronous Parallel Read Strobe. |
22 | PAR_CS | Low Enable. Asynchronous Parallel Chip Select. |
23 | GND | Connect to ground plane of board. |
24 | PAR_A3 | Parallel Address Bus Bit 3. |
25 | PAR_A1 | Parallel Address Bus Bit 1. |
26 | PAR_FS3 | Synchronous (PPI) Parallel Frame Sync 3. |
27 | PAR_FS1 | Synchronous (PPI) Parallel Frame Sync 1. |
28 | GND | Connect to ground plane of board. |
29 | SPORT_TDV0 | SPI Data Receive 3. (No connect.) 1 |
30 | SPORT_TDV1 | SPI Data Receive 2. (No connect.) 1 |
31 | SPORT_DR1 | SPORT Data Receive 1. Secondary SPORT Data into processor. |
32 | SPORT_DT1 | SPORT Data Transmit 1. Secondary SPORT Data from processor. |
33 | SPI_D2 | SPORT Data Transmit 2.(No connect.) 1 |
34 | SPI_D3 | SPORT Data Transmit 3.(No connect.) 1 |
35 | SERIAL_INT | Serial Interrupt. Used to trigger a non-periodic SPORT event. |
36 | GND | Connect to ground plane of board. |
37 | SPI_SEL_B | Low enable. SPI Chip Select B. Use this to control a second device on the SPI bus. |
38 | SPI_SEL_C | Low enable. SPI Chip Select C. Use this for a third device on the SPI bus. |
39 | SPI_SEL1/ SPI_SS | SPI Chip Select 1. 2 Used to connect to SPI Boot Flash if required. Also used as Chip Select when Blackfin processor is operating as SPI Slave. |
40 | GND | Connect to ground plane of board. |
41 | SDA_1 | I2C Data 1.2 |
42 | SCL_1 | I2C Data 1.2 |
43 | GPIO0 | General Purpose Input/Output. |
44 | GPIO2 | General Purpose Input/Output. |
45 | GPIO4 | General Purpose Input/Output. |
46 | GND | Connect to ground plane of board. |
47 | GPIO6 | General Purpose Input/Output.2 |
48 | TMR_A | Timer A flag pin. Use as first Timer if required. |
49 | TMR_C | Timer C flag pin.1 (No connect.) |
50 | NC | No Connect. Leave this pin unconnected. Do not ground. |
51 | NC | No Connect. Leave this pin unconnected. Do not ground. |
52 | GND | Connect to ground plane of board. |
53 | NC | No Connect. Leave this pin unconnected. Do not ground. |
54 | NC | No Connect. Leave this pin unconnected. Do not ground. |
55 | NC | No Connect. Leave this pin unconnected. Do not ground. |
56 | EEPROM_A0 | EEPROM A0. Connect to A0 Address line of the EEPROM |
57 | RESET_OUT | Active low pin to reset controller board. |
58 | GND | Connect to ground plane of board. |
59 | UART_RX | UART Receive Data.2 |
60 | RESET_IN | Active low pin to reset controller board. |
61 | BMODE1 | Boot Mode 1. Pull up with 10kΩ resistor to set SDP-B to boot from SPI Flash. Enabled on Connector A only. |
62 | UART_TX | UART Receive Data.2 |
63 | GND | Connect to ground plane of board. |
64 | SLEEP | Active low sleep from processor board. |
65 | WAKE | External wake up to processor board. |
66 | NC | No Connect. Leave this pin unconnected. Do not ground. |
67 | NC | No Connect. Leave this pin unconnected. Do not ground. |
68 | NC | No Connect. Leave this pin unconnected. Do not ground. |
69 | GND | Connect to ground plane of board. |
70 | NC | No Connect. Leave this pin unconnected. Do not ground. |
71 | CLKOUT | CLKOUT from processor. |
72 | TMR_D | Timer D flag pin.2 |
73 | TMR_B | Timer B flag pin. Use as second Timer if required. |
74 | GPIO7 | General Purpose Input/Output. |
75 | GND | Connect to ground plane of board. |
76 | GPIO5 | General Purpose Input/Output. |
77 | GPIO3 | General Purpose Input/Output. |
78 | GPIO1 | General Purpose Input/Output. |
79 | SCL_0 | I2C Clock 0. Daughter Board EEPROM must be connected to this bus. |
80 | SDA_0 | I2C Data 0. Daughter Board EEPROM must be connected to this bus. |
81 | GND | Connect to ground plane of board. |
82 | SPI_CLK | SPI Clock. |
83 | SPI_MISO | SPI Master In, Slave Out Data. |
84 | SPI_MOSI | SPI Master Out, Slave In Data. |
85 | SPI_SEL_A | SPI Chip Select A. Use this to control the first device on the SPI bus. |
86 | GND | Connect to ground plane of board. |
87 | SPORT_TSCLK | SPORT Transmit Clock. |
88 | SPORT_DT0 | SPORT Data Transmit 0. Primary SPORT Data from processor. |
89 | SPORT_TFS | SPORT Transmit Frame Sync. |
90 | SPORT_RFS | SPORT Receive Frame Sync. |
91 | SPORT_DR0 | SPORT Data Receive 0. Primary SPORT Data into processor. |
92 | SPORT_RSCLK | SPORT Receive Clock |
93 | GND | Connect to ground plane of board. |
94 | PAR_CLK | Clock for Synchronous Parallel Interface (PPI). |
95 | PAR_FS2 | Synchronous (PPI) Parallel Frame Sync 2. |
96 | PAR_A0 | Parallel Address Bus Bit 0. |
97 | PAR_A2 | Parallel Address Bus Bit 2. |
98 | GND | Connect to ground plane of board. |
99 | PAR_INT | Parallel Interrupt. Used to trigger a non-periodic Parallel event. |
100 | PAR_WR | Asynchronous Parallel Write Strobe. |
101 | PAR_D0 | Parallel Data Bus Bit 0. |
102 | PAR_D2 | Parallel Data Bus Bit 2. |
103 | PAR_D4 | Parallel Data Bus Bit 4. |
104 | GND | Connect to ground plane of board. |
105 | PAR_D6 | Parallel Data Bus Bit 6. |
106 | PAR_D8 | Parallel Data Bus Bit 8. |
107 | PAR_D10 | Parallel Data Bus Bit 10. |
108 | PAR_D12 | Parallel Data Bus Bit 12. |
109 | GND | Connect to ground plane of board. |
110 | PAR_D15 | Parallel Data Bus Bit 15. |
111 | PAR_D16 | Parallel Data Bus Bit 16. (No connect.) 1 |
112 | PAR_D18 | Parallel Data Bus Bit 18. (No connect.) 1 |
113 | PAR_D20 | Parallel Data Bus Bit 20. (No connect.) 1 |
114 | PAR_D22 | Parallel Data Bus Bit 22. (No connect.) 1 |
115 | GND | Connect to ground plane of board. |
116 | VIO(+3.3V) | +3.3V Output. 20mA max current available to power IO voltage on daughter board. |
117 | GND | Connect to ground plane of board. |
118 | GND | Connect to ground plane of board. |
119 | NC | No Connect. Leave this pin unconnected. Do not ground. |
120 | NC | No Connect. Leave this pin unconnected. Do not ground. |
1 Functionality not implemented on the SDP board 2 Shared across both connectors.
Each interface provided by the SDP-B is available on unique pins of the SDP-B’s 120 pin connector. The connector pin numbering scheme is out-line in Figure HWD2.
Pin No. | Pin Name | Description |
---|---|---|
C1 | GND | Ground |
C2 | DP0_C2M_P | No connect |
C3 | DP0_C2M_N | No connect |
C4 | GND | Ground |
C5 | GND | Ground |
C6 | DP0_M2C_P | No connect |
C7 | DP0_M2C_N | No connect |
C8 | GND | Ground |
C9 | GND | Ground |
C10 | LA06_P | User defined signals connected to FPGA bank 2 2 |
C11 | LA06_N | User defined signals connected to FPGA bank 2 2 |
C12 | GND | Ground |
C13 | GND | Ground |
C14 | LA10_P | User defined signals connected to FPGA bank 2 2 |
C15 | LA10_N | User defined signals connected to FPGA bank 2 2 |
C16 | GND | Ground |
C17 | GND | Ground |
C18 | LA14_P | User defined signals connected to FPGA bank 2 2 |
C19 | LA14_N | User defined signals connected to FPGA bank 2 2 |
C20 | GND | Ground |
C21 | GND | Ground |
C22 | LA18_P_CC | User defined signals connected to FPGA bank 2 2 |
C23 | LA18_N_CC | User defined signals connected to FPGA bank 2 2 |
C24 | GND | Ground |
C25 | GND | Ground |
C26 | LA27_P | User defined signals connected to FPGA bank 2 2 |
C27 | LA27_N | User defined signals connected to FPGA bank 2 2 |
C28 | GND | Ground |
C29 | GND | Ground |
C30 | SCL | I2C clock line for reading FMC EEPROM |
C31 | SDA | I2C data line for reading FMC EEPROM |
C32 | GND | Ground |
C33 | GND | Ground |
C34 | GA0 | I2C geographical address 0. Must be connected to address pin A1 of FMC EEPROM |
C35 | 12P0V | 12V (1 amp) power supply to daughterboard |
C36 | GND | Ground |
C37 | 12P0V | 12V (1 amp) power supply to daughterboard |
C38 | GND | Ground |
C39 | 3P3V | 3.3V (3 amp) power supply to daughterboard |
C40 | GND | Ground |
D1 | PGC2M | Active high signal indicating 12P0V, 3P3V and VADJ power supplies are turned on |
D2 | GND | Ground |
D3 | GND | Ground |
D4 | No connect | No connect |
D5 | No connect | No connect |
D6 | GND | Ground |
D7 | GND | Ground |
D8 | LA01_P_CC | User defined signals connected to FPGA bank 2 2 |
D9 | LA01_N_CC | User defined signals connected to FPGA bank 2 2 |
D10 | GND | Ground |
D11 | LA05_P | User defined signals connected to FPGA bank 2 2 |
D12 | LA05_N | User defined signals connected to FPGA bank 2 2 |
D13 | GND | Ground |
D14 | LA09_P | User defined signals connected to FPGA bank 2 2 |
D15 | LA09_N | User defined signals connected to FPGA bank 2 2 |
D16 | GND | Ground |
D17 | LA13_P | User defined signals connected to FPGA bank 2 2 |
D18 | LA13_N | User defined signals connected to FPGA bank 2 2 |
D19 | GND | Ground |
D20 | LA17_P_CC | User defined signals connected to FPGA bank 2 2 |
D21 | LA17_N_CC | User defined signals connected to FPGA bank 2 2 |
D22 | GND | Ground |
D23 | LA23_P | User defined signals connected to FPGA bank 2 2 |
D24 | LA23_N | User defined signals connected to FPGA bank 2 2 |
D25 | GND | Ground |
D26 | LA26_P | User defined signals connected to FPGA bank 2 2 |
D27 | LA26_N | User defined signals connected to FPGA bank 2 2 |
D28 | GND | Ground |
D29 | TCK | JTAG clock |
D30 | TDI | JTAG data input |
D31 | TD0 | JTAG data output |
D32 | 3P3VAUX | 3.3V (20 milliAmp) power supply for powering only the FMC EEPROM |
D33 | TMS | JTAG mode select |
D34 | TRST_L | JTAG reset |
D35 | GA1 | I2C geographical address 1. Must be connected to address pin A0 of FMC EEPROM |
D36 | 3P3V | 3.3V (3 amp) power supply to daughterboard |
D37 | GND | Ground |
D38 | 3P3V | 3.3V (3 amp) power supply to daughterboard |
D39 | GND | Ground |
D40 | 3P3V | 3.3V (3 amp) power supply to daughterboard |
G1 | GND | Ground |
G2 | CLK1_M2C_P | Positive line of differential pair for carrying clock signals from daughterboard |
G3 | CLK1_M2C_N | Negative line of differential pair for carrying clock signals from daughterboard |
G4 | GND | Ground |
G5 | GND | Ground |
G6 | LA00_P_CC | User defined signals connected to FPGA bank 2 2,3 |
G7 | LA00_N_CC | User defined signals connected to FPGA bank 2 2,3 |
G8 | GND | Ground |
G9 | LA03_P | User defined signals connected to FPGA bank 2 2 |
G10 | LA03_N | User defined signals connected to FPGA bank 2 2 |
G11 | GND | Ground |
G12 | LA08_P | User defined signals connected to FPGA bank 2 2 |
G13 | LA08_N | User defined signals connected to FPGA bank 2 2 |
G14 | GND | Ground |
G15 | LA12_P | User defined signals connected to FPGA bank 2 2 |
G16 | LA12_N | User defined signals connected to FPGA bank 2 2 |
G17 | GND | Ground |
G18 | LA16_P | User defined signals connected to FPGA bank 2 2 |
G19 | LA16_N | User defined signals connected to FPGA bank 2 2 |
G20 | GND | Ground |
G21 | LA20_P | User defined signals connected to FPGA bank 2 2 |
G22 | LA20_N | User defined signals connected to FPGA bank 2 2 |
G23 | GND | Ground |
G24 | LA22_P | User defined signals connected to FPGA bank 2 2 |
G25 | LA22_N | User defined signals connected to FPGA bank 2 2 |
G26 | GND | Ground |
G27 | LA25_P | User defined signals connected to FPGA bank 2 2 |
G28 | LA25_N | User defined signals connected to FPGA bank 2 2 |
G29 | GND | Ground |
G30 | LA29_P | User defined signals connected to FPGA bank 2 2 |
G31 | LA29_N | User defined signals connected to FPGA bank 2 2 |
G32 | GND | Ground |
G33 | LA31_P | User defined signals connected to FPGA bank 2 2 |
G34 | LA31_N | User defined signals connected to FPGA bank 2 2 |
G35 | GND | Ground |
G36 | LA33_P | User defined signals connected to FPGA bank 2 2 |
G37 | LA33_N | User defined signals connected to FPGA bank 2 2 |
G38 | GND | Ground |
G39 | VADJ | Variable (1.2V to 3.3V) (2 amps) power supply to daughterboard |
G40 | GND | Ground |
H1 | No connect | No connect |
H2 | PRSNT_M2C_L | Indicates presence of daughterboard. Must be tied to ground on daughterboard |
H3 | GND | Ground |
H4 | CLK0_M2C_P | Positive line of differential pair for carrying clock signals from daughterboard |
H5 | CLK0_M2C_N | Negative line of differential pair for carrying clock signals from daughterboard |
H6 | GND | Ground |
H7 | LA02_P | User defined signals connected to FPGA bank 2 2 |
H8 | LA02_N | User defined signals connected to FPGA bank 2 2 |
H9 | GND | Ground |
H10 | LA04_P | User defined signals connected to FPGA bank 2 2 |
H11 | LA04_N | User defined signals connected to FPGA bank 2 2 |
H12 | GND | Ground |
H13 | LA07_P | User defined signals connected to FPGA bank 2 2 |
H14 | LA07_N | User defined signals connected to FPGA bank 2 2 |
H15 | GND | Ground |
H16 | LA11_P | User defined signals connected to FPGA bank 2 2 |
H17 | LA11_N | User defined signals connected to FPGA bank 2 2 |
H18 | GND | Ground |
H19 | LA15_P | User defined signals connected to FPGA bank 2 2 |
H20 | LA15_N | User defined signals connected to FPGA bank 2 2 |
H21 | GND | Ground |
H22 | LA19_P | User defined signals connected to FPGA bank 2 2 |
H23 | LA19_N | User defined signals connected to FPGA bank 2 2 |
H24 | GND | Ground |
H25 | LA21_P | User defined signals connected to FPGA bank 2 2 |
H26 | LA21_N | User defined signals connected to FPGA bank 2 2 |
H27 | GND | Ground |
H28 | LA24_P | User defined signals connected to FPGA bank 2 2 |
H29 | LA24_N | User defined signals connected to FPGA bank 2 2 |
H30 | GND | Ground |
H31 | LA28_P | User defined signals connected to FPGA bank 2 2 |
H32 | LA28_N | User defined signals connected to FPGA bank 2 2 |
H33 | GND | Ground |
H34 | LA30_P | User defined signals connected to FPGA bank 2 2 |
H35 | LA30_N | User defined signals connected to FPGA bank 2 2 |
H36 | GND | Ground |
H37 | LA32_P | User defined signals connected to FPGA bank 2 2 |
H38 | LA32_N | User defined signals connected to FPGA bank 2 2 |
H39 | GND | Ground |
H40 | VADJ | Variable (1.2V to 3.3V) (2 amps) power supply to daughterboard |
2 User defined signals with “P” suffix can be used as the positive pin of the differential pair. User defined signals with “N” suffix can be used as the negative pin of the differential pair. For further information see the VITA 57 specification.
3 User defined signals with “CC” suffix are the preferred signal lines on which to transmit clock signals from the controller board to the daughterboard. They are connected to global clock lines on the FPGA but they can also be used to carry any other user defined signal. For further information see the VITA 57 spec
The SDP-H1 must be powered using the enclosed 12V 30W wall-wart power supply. This 12V supply is converted, using on-board DC/DC switching regulators, to power all on-board systems as well as supply power to any daughterboard connected to the FMC connector. The table below outlines the voltage and currents available to daughterboards connected to the FMC connector (as required by the VITA 57 specification). Please note that the maximum allowed power budget for the daughterboard is 10W (for further information see the VITA 57 specification).
Voltage Supply | Voltage Range | Number of Pins | Max Current | Tolerance |
---|---|---|---|---|
VADJ | 1.2-3.3V | 2 | 2 A | +/- 5% |
3P3VAUX | 3.3V | 1 | 20 mA | +/- 5% |
3P3VAUX | 3.3V | 4 | 3 A | +/- 5% |
12P0V | 12V | 2 | 1 A | +/- 5% |
The SDP-H1 board also provides 3.3V at 20mA on Pin 116 (VIO_3.3) to connected daughter boards as the VIO voltage for the daughter board. Pin 5 (USB_VBUS) is connected to an internal 5V power supply, providing 5V ±10% as an output of the SDP board.
The mechanical specifications of the SDP-H1 board are 4.33“ × 4.17” (110 mm × 106 mm). The height of the 120-pin connect-ors from the bottom of the board is approximately 0.152“ (3.86 mm). The height of the FMC-LPC connector from the top of the board is approximately 0.258” (6.55 mm). The tallest component on the top is the DC power input connector at approximately 0.433” (11 mm) and the tallest component on the bottom is the inductor L9 at approximately 0.157“ (4 mm) (The rubber feet on the bottom of the board are 0.311” (7.9mm) tall).
Figure HWD2 : SDP-H1 Dimensions
Figure HWD3 : SDP-H1 Vertical height
Figure HWD4 : SDP-H1 Bottom of SDP-H1