Differences
This shows you the differences between two versions of the page.
|
resources:eval:sdp:sdp-b:peripherals:twi [18 May 2011 15:23] Jean McAdam created |
resources:eval:sdp:sdp-b:peripherals:twi [12 Sep 2011 15:54] Jean McAdam Approved |
||
|---|---|---|---|
| Line 2: | Line 2: | ||
| The TWI / I<sup>2</sup>C bus is fully compatible with the widely used I<sup>2</sup>C bus standard as defined by Philips I<sup>2</sup>C Bus Specification version 2.1. \\ | The TWI / I<sup>2</sup>C bus is fully compatible with the widely used I<sup>2</sup>C bus standard as defined by Philips I<sup>2</sup>C Bus Specification version 2.1. \\ | ||
| - | Pull up Resistors are required on both the SDA and SCL lines, so the lines will idle high at all times. | + | Pull up Resistors are present on both the SDA and SCL lines, so the lines will idle high at all times. |
| - | \\ Data Rates :up to 100K bits/second (Standard Mode)and up to 400K bits/second (Fast Mode)data rates | + | \\ Data Rates:up to 100K bits/second (Standard Mode)and up to 400K bits/second (Fast Mode)data rates |
| ^Pin Blackfin Name^Pin SDP 120 Pin Connector Name ^ Description ^ | ^Pin Blackfin Name^Pin SDP 120 Pin Connector Name ^ Description ^ | ||
| - | |SDA|SDA_0|In/ Out TWI serial data, high impedance reset value| | + | |SDA|SDA_0|In/Out TWI serial data, high impedance reset value| |
| |SCL|SCL_0|In/Out TWI serial clock, high impedance reset value| | |SCL|SCL_0|In/Out TWI serial clock, high impedance reset value| | ||
| Table 1: I<sup>2</sup>C Pin Assignments | Table 1: I<sup>2</sup>C Pin Assignments | ||
resources/eval/sdp/sdp-b/peripherals/twi.txt · Last modified: 12 Sep 2011 15:54 by Jean McAdam