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This version (18 May 2011 15:39) was approved by jeanmca.

PPI: Parallel Peripheral Interface

PPI is a half-duplex, bi-directional port accommodating up to 16 bits of data. It has a dedicated clock pin and three multiplexed frame sync pins. PPI supports up to 16 bits of data with programmable clock and frame sync polarities. PPI requires an externally generated free running clock.
The maximum PPI Clock Frequency achievable on the SDP for a single frame transfer is 50MHz. The maximum transfer rate on SDP for streaming data over the PPI is achievable by using a 20-25 MHz PPI clock.

Pin - Blackfin NamePin - SDP 120 Pin Connector NameDescription
PPI_CLKPAR_CLKPPI Clock
PPI_FS1PAR_FS1PPI Frame Sync 1
PPI_FS2PAR_FS2PPI Frame Sync 2
PPI_FS3PAR_FS3PPI Frame Sync 3
PPI_D0PAR_D0PPI Data 0
PPI_D1PAR_D1PPI Data 1
PPI_D2PAR_D2PPI Data 2
PPI_D3PAR_D3PPI Data 3
PPI_D4PAR_D4PPI Data 4
PPI_D5PAR_D5PPI Data 5
PPI_D6PAR_D6PPI Data 6
PPI_D7PAR_D7PPI Data 7
PPI_D8PAR_D8PPI Data 8
PPI_D9PAR_D9PPI Data 9
PPI_D10PAR_D10PPI Data 10
PPI_D11PAR_D11PPI Data 11
PPI_D12PAR_D12PPI Data 12
PPI_D13PAR_D13PPI Data 13
PPI_D14PAR_D14PPI Data 14
PPI_D15PAR_D15PPI Data 15

Table 1 : Pin Assignments

The maximum transfer rate is entirely dependent on the PC performance, so can vary depending on the other software tasks running at teh same time. The USB transfer rate can also vary as a result of the CPU workload so the frame sync length across the PPI interface can vary accordingly.
The PPI interface requires an external source to generate a free running clock and implement some flow control.

Figure 1 : PPI Interface connection to receive data

A maximum of 32k words of 16 bits per frame (PPI_FS1) can be sent in each PPI transfer. The SDP board controls the transfer through the implementation of a second frame called Master Ready (PPI_FS2-MR). This enables, or stops, the data transfer from the FPGA or external source. If the SDP internal buffer structure is full or the USB connection is very slow, the MR signal goes low and will pause the data transfer. Otherwise, MR is active and a new PPI_FS1 signal is generated.


Figure 2 : PPI Transfer Protocol

Asynchronous Parallel

The Asynchronous memory interface is available through the External Bus Interface Unit (EBIU). The Asynchronous Memory Bank made available is from 0x20000000 to 0x200FFFFF. The EBIU is clocked by the System Clock, SCLK, which runs at 120MHz.

Pin - Blackfin NamePin - SDP 120 Pin Connector NameDescription
/ARE/PAR_RDAsynchronous Read Enable
/AWE/PAR_WRAsynchronous Write Enable
/AMS0/PAR_CSAsynchronous Memory Bank Select
PG9PAR_INTAsynchronous Interrupt
A1PAR_A0External Address Bus
A2PAR_A1External Address Bus
A3PAR_A2External Address Bus
A4PAR_A3External Address Bus
D0PAR_D0External Data Bus
D1PAR_D1External Data Bus
D2PAR_D2External Data Bus
D3PAR_D3External Data Bus
D4PAR_D4External Data Bus
D5PAR_D5External Data Bus
D6PAR_D6External Data Bus
D7PAR_D7External Data Bus
D8PAR_D8External Data Bus
D9PAR_D9External Data Bus
D10PAR_D10External Data Bus
D11PAR_D11External Data Bus
D12PAR_D12External Data Bus
D13PAR_D13External Data Bus
D14PAR_D14External Data Bus
D15PAR_D15External Data Bus


Table 2:Asynchronour Parallel Pin Assignment


Figure 3 : Asynchronous Write Followed by a Read

resources/eval/sdp/sdp-b/peripherals/ppi.txt · Last modified: 18 May 2011 15:39 by jeanmca