EVALUATING THE HMCAD1511/HMCAD1520 ANALOG-TO-DIGITAL CONVERTERS
Preface
This user guide describes the HMCAD1520-EBZ and HMCAD1511-EBZ evaluation boards, which provide the support circuitry required to operate the HMCAD1520 and HMCAD1511 in its various modes and configurations. The application software used to interface with the device is also described.
This guide shows how HMCAD15XX-EBZ works with the SDP-H1 (EVAL-SDP-CH1Z) controller board developed by Analog Devices. Link to the previous user guide document is provided for customers who still have the old evaluation system developed by Hittite which uses the Xilinx SP-601 controller board.
Typical Setup
Figure 1. HMCAD15xx-EBZ (left) and EVAL-SDP-CH1Z (right) Setup
Tip: Click on any picture in this guide to open an enlarged version.
Helpful Files
Software Needed:
Hardware Needed:
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12Vdc 1A Wall Adapter for SDP-H1
PC with ACE and Visual Analog Software Applications
(2) High-Frequency Continuous Wave Generator (Clock and Analog Input Source)
(2) SMA Cables
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Bandpass Filter
Evaluation Board Hardware
HMCAD1520-EBZ /HMCAD1511-EBZ evaluation board has four input channels that supports single-ended to differential conversion with the use of a balun. By default, all input channels 1-4 (SMAs J3, J5, J6 and J7) are balun-coupled. Alternatively, input channel 1 (SMAs J3 and J4) can be configured to differential to differential conversion, and input channel 2 (SMA J5) can be configured to single-ended to differential conversion using the onboard LTC6419 high-speed differential ADC driver. Moreover, results for optional amplifier configuration can be seen in Optional Amplifier Configuration Results.
Refer to the table below for the optional amplifier configuration.
Analog Input Channel Number | Default Input Driver, AC/DC coupling | Signal type on Input/Output | Install | Uninstall |
1 | LTC6419, DC coupling, Unity Gain | Differential/Differential | R41, R42, R44, R45, R60, R61 | C51, C52, R23, R24, R56, R57 |
2 | LTC6419, DC coupling, Unity Gain | Single-Ended/Differential | R46, R58, R59 | C53, R54, R55, R23, R24 |
The HMCAD1520/HMCAD1511 supplies the common-mode voltage at half-supply (0.9V) for all the analog input channels. No external supply is needed for the input Vcm.
Clocking
The HMCAD1520-EBZ evaluation board uses an external clock source on SMA J1 as default.
On the other hand, the HMCAD1511-EBZ evaluation board has an on-board 1GHz crystal for clocking the HMCAD1511. The user can also configure the board to use an external clock source for the HMCAD1511-EBZ board.
Refer to the table below for alternative clock configuration.
Clock Configuration | Install | Uninstall |
Onboard | R13 | R12 |
External | R12 | R13 |
Power Supply
Both the HMCAD1520 and HMCAD1511 were being supplied by ADM7154 with 1.8V. The board can be modified to bypass the LDO so the HMCAD1520 and HMCAD1511 are directly supplied by the LTM8078 DC-DC regulator. To do this, change components C3 to 100uF, R6 to 200k, and install a ferrite bead to R9. Also, uninstall R8 and R10.
The supply rails for other components on the board (crystal, amplifier, etc) are isolated to the HMCAD1520 and HMCAD1511 supply rail. Refer to the board schematics for more info.
Quick Start Guide
The following procedure below shows how to setup the evaluation board to capture 70MHz input signal at 1GSPS sampling rate:
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Connect the SDP-H1 to PC via
USB and to a 12V 1A power supply.
Open ACE, the evaluation board will automatically be recognized by the software. Otherwise, install the plugin for HMCAD1511/20 evaluation board.
In ACE, go to Plug-in Manager.
Under Available Packages, search HMCAD1520 then click install.
Double click the
HMCAD1511/HMCAD1520 Board and then double click the
HMCAD1511/HMCAD1520 blue chip. The onboard green LED should light up (DS1), indicating power is already supplied, and red LED (LED0) of SDP-H1 will start blinking.

Figure 2. HMCAD1511/20-EBZ ACE Board View Window
Make sure that the state of the board is good (State=Good), check on the bottom-left corner.
Configure the initialization wizard settings shown in Figure 3. For
HMCAD1511-EBZ, select
External Clock as clock source and input
1GHz on the CLKIN.
Figure 3. HMCAD1511-EBZ Initialization Wizard Settings
Connect a continuous wave generator as an input signal on SMA
J7 with a frequency of
70MHz.
Use a bandpass filter in between the signal source and the SMA connector.
For
HMCAD1511-EBZ, connect another continuous wave generator as the ADC clock. Set the clock frequency to
1GHz and
10dBm output level.
Going back to ACE Software, click Proceed to Analysis button and click on the FFT tab. Click Run Once button under Capture wizard to capture an FFT plot.
Observe the fundamental frequency and power. Adjust the signal source until fundamental power obtains approximately -1dBFS at 70MHz.
Figure 4. HMCAD1511-EBZ Fundamental Frequency and Power
If fundamental power achieved, click
Zoom to Fit (

) to show graph at Fs/2, then click
Show Annotations (

) to show all the spurs' annotation within the plot. Refer to Figure 5.
Figure 5. HMCAD1511-EBZ (8-bit, single channel, Fs=1GHz, Fin=70MHz) FFT Analysis Results
To save the
Data Set, click
Export button on the
Results wizard. Also, you click
Import button to review the saved data set with a file format of “
.acesamples”.
Table 3. HMCAD1511-EBZ (8-bit, single channel, Fs=1GHz, Fin=70MHz) Results Comparison.
Note: SDP-H1 is limited to operate Fin<375MHz.
If Spur_x is equal to Harm_x, then harmonic spectral power is removed and is set to -300dBc.
If the result is a little bit poor due to calculation rounding-off, increase at least 2 bins at harmonic bins settings.
Interleaving Spurs Calculation
You can download the
HMCAD15xx-EBZ Interleaving Spurs Calculator in the
Helpful Files, and input both the sampling and input frequencies on the yellow boxes provided. The calculator will provide the spur frequencies depending on the selected number of channels. In figure 6, the analog input signal is around
70MHz with different sampling rate.
Figure 6. HMCAD1511-EBZ ACE vs Interleaving Spurs Calculator
Optional Amplifier Configuration Results
This section is intended to provide evaluation board characterization results on Differential-to-Differential configuration in Channel 1 using the LTC6419 amplifier as shown in Figure 7, and on Single-to-Differential configuration in Channel 2 using the said amplifier as shown in Figure 8.
Figure 7. Amplifier Path for Differential-to-Differential Configuration in CH1
Figure 8. Amplifier Path for Single-to-Differential Configuration in CH2
Troubleshooting Tips
If the FFT window remains blank after Running Once in ACE, do the following:
Make sure there is a clock signal going to the ADC.
Check the 1.8V supply rails of the ADC. The onboard yellow LED indicates 12V is being supplied to the board.
Check if there's no error messages in ACE. If there is any, power cycle the board and restart the ACE software.
Make sure the SDP-H1 board is powered up and connected to the PC via
USB.
If the FFT plot appears abnormal, do the following:
Make sure that the input signal is not overdriving the ADC. Limit the fundamental frequency to -1dBFS.
Check for the Vcm at the analog input path. The Vcm should be around 0.9V.
Make sure that the correct encoding is set in ACE. The default setting is Twos complement.
Check for any loose connections between the input SMA and the signal source. Same with the clock source if using an external clock.
If using the LTC6419 as the ADC driver, check the 5V supply rail and the 0.9V common mode voltage.
Make sure the correct resolution and channel configuration are set correctly on ACE.
If the FFT plot still appears distorted or does not produce a capture after following the steps above, do the following steps below:
Check the path C:\ProgramData\Analog Devices\ACE\Plugins\Board.HMCAD1520.1.2022…\content\FpgaImages if this exists.
If yes, check if there is hmcad_sdph1.bit file inside the FPGA Images folder and if so, exclude the bit file inside.
Look for an appropriate FPGA image
hmcad_sdph1_xxxdeg folder in the
Helpful Files, copy it into the FPGA Images folder in the path, and rename it to
hmcad_sdph1.bit.
Run the ACE software and proceed with the analysis. If running the FPGA image and still will not produce a good data capture, repeat the steps above until selected FPGA image will produce a good data capture. You may refer to the
HMCAD15xx SDP-H1 Phase DDR pptx slides in the
Helpful Files.
If after running all the FPGA images and still not produce a good data capture, contact the responsible applications engineer.
If the FFT plot appears normal but performance is poor, do the following:
Make sure that an appropriate analog filter is used on the input signal.
Make sure that the fundamental frequency is set to -1dBFS.
Make sure that the signal generators for the clock and the analog input are clean (low phase noise).
Make sure the correct resolution and channel configuration are set correctly on ACE.
If the ACE cannot detect the board or prompts an error message during data capture, do the following:
Make sure the SDP-H1 is powered correctly and connected to the PC via
USB.
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