The EVAL-AD79XXEDZ is an evaluation board for the 20-lead AD7944 (14-bit), AD7985 (16-bit), and AD7986 (18-bit) PulSAR® analog-to-digital converters (ADCs). On-board components include a high precision, buffered band gap 5.0 V reference (ADR435), reference buffers (AD8032), a signal conditioning circuit with two op amps (AD8021), and an FPGA for deserializing the serial conversion results. The evaluation board interfaces to the CED capture board by using a 96-pin DIN connector. In addition, SMB connectors, J1 and J2, are provided for the low noise analog signal source.
Note that the measurements made by Analog Devices use the Audio Precision SYS-2522.
The low power, AD7944/AD7985/AD7986 ADCs offer very high performance of up to 2.0 MSPS (AD7986) and 2.5 MSPS (AD7944 and AD7985) throughput rates using a flexible parallel interface on the 96-pin interface to the EVAL-CED1Z board.
The evaluation board is designed to demonstrate the performance of the ADC and to provide an easy-to-understand interface for a variety of system applications.
The evaluation board is ideal for use with the Analog Devices Converter and Evaluation Development EVAL-CED1Z (CED). The design offers the flexibility of applying external control signals and is capable of generating conversion results on parallel 16-bit wide buffered outputs.
Figure 2 shows the EVAL-AD7944/AD7985/AD7986EBZ evaluation board. The on-board FPGA, U3, provides the necessary control signals for conversion and deserializes the serial data as the EVAL-CED1Z board uses a parallel interface. The evaluation board is a flexible design that enables the user to choose among many different board configurations, analog signal conditioning, reference, and different modes of conversion data.
This evaluation board is a 6-layer board carefully laid out and tested to demonstrate the specific high accuracy performance of the AD7944, AD7985, and AD7986. See the Design Support Package section for the board schematic and layout.
These ADCs are low power and high speed and include an internal conversion clock, an internal reference (and buffer), error correction circuits, and a versatile serial interface port. On the rising edge of CNV, the ADC samples an analog input, IN+, between 0 V and REF with respect to the ground sense, IN−. The ADCs feature a very high sampling rate turbo mode (TURBO is high) and a reduced power normal mode (TURBO is low) for low power applications where the power is scaled with the throughput. A full description of these products is available in their respective data sheets and should be consulted when using this evaluation board.
Power is supplied to the board through P1 when used with the EVAL-CED1Z. Each supply is decoupled at the point where it enters the board and again at each device. A single ground plane on this board minimizes the effect of high frequency noise interference.
The evaluation board can be used in standalone mode without the CED controller board. In this case, power supplies need to be applied to the board at P4 or at the relevant test points. At a minimum, the board requires ±5 V, +12 V, +7 V, or + 2.5 V. See the Design Support Package section for details regarding power supply connections.
The evaluation board ground plane is separated into two sections: a plane for the digital interface circuitry and an analog plane for the analog input and external reference circuitry. To attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths by connecting the planes together directly under the converter.
The on-board FPGA performs a number of digital functions, one of them being the deserialization of the serial conversion results as the CED data capture board uses a 16-bit parallel interface. If desired, the deserialized data can be monitored on the 96-pin edge connecter, P1, BD[15:0]. The CED uses a buffered busy signal, BBUSY, as the general interrupt for data.
The analog inputs to the evaluation board are J1, J2, and SMB (push on). These inputs are buffered with dedicated amplifier circuitry (A2, A3, and discretes) to allow configuration changes such as positive or negative gain, input range scaling, filtering, addition of a dc component, and use of different op amps and supplies. The analog input amplifiers are set as unity-gain buffers at the factory. The supplies are selectable with solder pads and are set for the +7 V to −5 V ranges.
The default configuration sets both A2 and A3 at midscale generated from either a buffered reference voltage divider or the internal reference of the ADC.
The evaluation board is factory configured for providing either a single-ended path or a fully differential path. Because the AD7986 is differential, both inputs and amplifier circuits are used to buffer the IN+ and IN- inputs of the ADCs. For the AD7944 and AD7985 evaluation boards, only the J2, A3, and associated circuitry is used in the path.
For dynamic performance, an FFT test can be executed by applying a very low distortion ac source. For low frequency testing, an audio precision source can be used directly because the outputs on these are isolated. Set the audio precision outputs for balanced and floating. Although different sources can be used, most are single ended and use a fixed output resistance.
Because the evaluation board uses the amplifiers in unity gain, the noninverting input has a common-mode input with a 590 Ω series resistor, which needs to be taken into account when directly connecting a source (voltage divider).
The 3-wire serial interface SDI, SCK, and SDO together with CNV are present on the digital interface test points, and FPGA buffered versions are on the 96-pin connector, P1. The on-board Altera FPGA can be reprogrammed to the user’s configuration as the serial device and U1 is in-circuit programmable.
A number of 3-pin jumpers, solder pads, and test points are provided on the evaluation board and are detailed in Table 1, Table 2, and Table 7. Most of the 3-pin jumpers are used for the reference selection of the ADCs (see the Reference Options section for details and settings).
|P2||REF to middle||ADC REF/REFIN select|
|P9||REFS to VREF||On-board reference/external reference selection|
|P10||BUF to middle||Selection of either Amplifier U2 or bypassing.|
|P11||REFIN to GND||Selection of either the internal reference and/or reference buffer. Used in conjunction with P12 and P9.|
|P12||PDREF to VIO||Selection of either the internal reference of the ADC or an external reference.|
|Solder Pad||Default Position||Function|
|JP1, JP2||A2, A3 (bottom to middle)||ADC inputs: bottom pad to middle pad are for A2/A3 output. To bypass and use J1/J2 directly, solder top pad to middle pad.|
|JP3||ADC specific||Single or differential ADC input selection. Top pad to middle pad for the AD7986; bottom pad to middle pad for AD7944 and the AD7985.|
|JP9, JP10||Left pads||10-lead or 20-lead amplifier to ADC selection for future use.|
|VDRV−||−5 VA||Buffer amplifier negative supply: Selection of GND or −5 VA.|
|VDRV+||+7 V||Buffer amplifier positive supply: selection of 12 V, 7 V, or 5 V.|
|VCC REF||+7 V||Reference circuit positive supply: selection of 12 V or 7 V.|
|AVDD||+2.5 V||ADC AVDD (analog core) supply: selection of 2.5 V or 5 V on the board or externally. To prevent permanent damage to the ADC, do not solder to 5 V or connect this supply to > 2.5 V.|
|DVDD||+2.5 V||ADC DVDD (digital core) supply: selection of 2.5 V or 5 V on the board or externally. To prevent permanent damage to the ADC, do not solder to 5 V or connect this supply to > 2.5 V.|
|BVDD||+5 V||ADC BVDD 5 V supply: selection of 5 V on the board or externally. For an external reference, the best performance is obtained when the reference source that is connected to the REF pins and BVDD are the same. See the External Reference: Factory Configuration section for details.|
|VIO||+2.5 V||ADC digital input/output supply voltage.|
Solder pads are factory configured for the device being evaluated.
The AD7944/AD7985/AD7986 each have an internal 4.096 V reference together with an internal buffer useful for using an external reference, or it can use an external 5.0 V reference directly. The evaluation board can be configured to use any of these references. A number of jumpers are used to set the reference and are detailed in Table 3.
The evaluation board includes the ADR435 which is a 5 V precision voltage reference. This reference can drive the ADCs and the REF pin directly or it can be buffered with the AD8032; both of which serve as the factory default setting. The best attainable SNR is achieved by using the maximum reference voltage of 5 V (see the appropriate ADC datasheet for details).
|P2||REF and middle|
|P9||REFS to VREF|
|P10||BUF to middle|
|P11||REFIN to GND|
|P12||PDREF to VIO|
|BVDD||5 V (factory default)|
To use an external reference source as opposed to the internal reference, there are two methods available, as follows:
The evaluation board includes a 5 V source for the ADC reference supply, BVDD, set with a pair of solder pads of either 5 V or EXT_B, and a test point, EXT_B. For the best performance, derive this supply from the external reference. To use the EXT_B, remove the solder from the 5 V pad and solder the EXT_B pad to BVDD.
The ADC has an internal 4.096 V precision reference and can be used on most applications. Connecting PDREF to GND enables the internal reference. When the internal reference is enabled, 4.096 V as well as a 1.2 V band gap are present on the ADC REF pin and test point. Note when using the internal reference, external sources must not be connected to these test points because they are directly connected to the ADC pins.
|P9||REFS to VREF|
|P12||PDREF to GND|
|BVDD||5 V (factory)|
The internal reference buffer is useful when using an external 1.2 V reference. When using the internal reference buffer, applying 1.2 V to REFIN, which is directly connected to the REFIN pin of the ADC, produces 4.096 V at the REF pin of the ADC. Because there is no 1.2 V reference on the board, there are two methods to generate a 1.2 V reference. The first method is to connect an external source to the REFIN test point using the jumper settings listed in Table 5.
|P12||PDREF to VIO|
|BVDD||5 V (factory default)|
The second method is to use the U2 op amp to voltage divide down the 5 V output of the ADR435 to 1.2 V by using R2/R4 = 1 kΩ/316 Ω. To use this method, replace R4 and set the jumpers to the settings listed in Table 6.
|P2||REFIN to middle|
|P9||REFS to VREF|
|P10||BUF to middle|
|P11||REFIN to Pin 1|
|P12||PDREF to VIO|
|BVDD||5 V (factory default)|
The EVAL-CED1Z board must not be connected to the USB port of the PC until after the software is installed. However, to check that the board has power (evidenced by the green LED light being lit), the 7 V dc supply can be connected to the power input connector on the EVAL-CED1Z.
It is recommended to close all Windows® applications prior to installing the software.
The evaluation board comes with a CD as part of the evaluation kit. The latest software versions are always available from the Analog Devices product page, visit www.analog.com. Note that the user must accept the license agreement during the installation process.
After downloading the software, it is recommended to use the WinZip extract function to extract all of the necessary components rather than immediately selecting setup.exe from within the zipped file.
After extracting the software, click setup.exe in the folder created during the extraction process and follow the instructions on the screen.
If another version of the software already exists on the computer, it may be necessary to remove it. To remove prior versions of the software, click the Windows Start button, select Control Panel, and then select Add or Remove Programs. When the list populates, navigate to Analog Devices High Resolution sampling ADC’s Evaluation Software or PulSAR Evaluation Software and select Remove.
The software also installs the necessary USB drivers through a separate installation process. When the software installation completes the drivers installation wizard displays: click Install to install the drivers automatically, as shown in Figure 8 and Figure 9.
After installing the software and drivers, power the CED board and connect it to the PC USB 2.0 port, at which time the Welcome to the Found New Hardware Wizard initiates. Figure 10. Found New Hardware
When installed properly, the hardware wizard displays the following message, shown in Figure 11, signaling that the evaluation board software is setup and ready to use. Figure 11. Evaluation Board Software Installation Complete
On some PCs, the Found New hardware Wizard may show up again and, if so, follow the same procedure to install it properly. Use the Device Manager, shown in Figure 12, to verify that the driver was installed correctly. Figure 12. Device Manager Verification
If the driver was not installed properly, Windows does not recognize the CEDIZ board and the Device Manager menu displays a question mark for Other devices. Figure 13. Device Manager Menu Displaying Unrecognized Device
The most usual reason for uninstalled properties is caused by the installation of the software and drivers by a user without administrative privileges. If this is the case, log on as an administrator with full privileges and reinstall the software.
The evaluation board includes software for analyzing the AD7944, AD7985, and AD7986. The EVAL-CED1Z is required when using the software. Use the software to perform the following tests:
The software is located at <local_drive>:\Program Files\Analog Devices\PulSAR ADC Evaluation Software\Eval PulSAR CED.exe. A shortcut is also added to the Windows Start menu under Analog Devices PulSAR Evaluation Software, Eval PulSAR CED. To run the software, select the program from either location.
The evaluation board includes software for analyzing the AD7944, AD7985, and AD7986 ADCs. The EVAL-CED1Z is required when using the ADC analysis software. Use the software to perform the following tests:
Refer to Figure 15 to Figure 20 for additional details and features of the software.
The ADC analysis software is located at C:\Program Files\Analog Devices\ PulSAR ADC Evaluation Software\Eval PulSAR CED.exe. A shortcut is also added to the Windows Start menu under Analog Devices PulSAR ADC Evaluation Software, Eval PulSAR CED. To run the software, select the program from either location.
The following steps detail the operation of the software located in the default directory: <local_drive>:\Program Files\Analog Devices\PulSAR ADC Evaluation Software\Eval PulSAR CED.exe, which opens the Raw Data Capture window.
To use the on-screen help. Select Help, Show Context Help or click Help (F1). These function areas on the screen are indicated by Number 1 in Figure 16. Hovering the cursor over most screen items displays useful information for the particular control or displayed unit.
The histogram controls, shown in the area indicated by Number 2 in Figure 16, are used for axes and zooming panning, as follows:
Locks the graph axis to automatically fit the data.
Uses the last axis set by the user. These allow the user to rescale the x- and y-axis, respectively, to the automatic values.
These are used to set the x- and y-axis properties, such as format, precision, color, and so forth.
Displays the cursor.
Zooms in and out.
Use to pan.
Sets various graph properties such as graph type, colors, lines, and so forth.
The areas of the Raw Data Capture window that pertain to working with histogram or oscilloscope charts are demarcated by the sections numbered 1, 2, and 3 in Figure 17.
Use the buttons shown in Section 1 in Figure 17 to perform either a single capture or continuous capture of data. Enter the number of samples that are required in the # of Samples (k) field (located to the left of the Single Capture (F3) button). The statistics for the x- and y-axes are displayed in the Histogram Data section of the window, shown as the Number 2 and Number 3 areas within Figure 17.
The graphic results are displayed in the chart area of the window. Note that the results can be displayed as either a histogram (see Figure 18) or an oscilloscope (see Figure 19) by selecting the relevant tab, Oscilloscope, above the chart display (shown as Number 1 in Figure 20).
Time domain data can also be viewed by using the Oscilloscope tab. In addition, the charts can be displayed together when the Summary tab is selected (see Figure 21).
To review the FFT spectrum data, select the Spectrum tab in the Raw Data Capture window. Figure 22 shows the FFT spectrum window and sections numbered 1, 2, and 3 of this window are described as follows:
From the Raw Data Capture window, in the section of Figure 22 labeled with Number 1, select the Spectrum tab to display the FFT when the spectrum chart is selected.
The Spectrum Data section (Number 2 and Number 3 in Figure 22), is located beneath the spectrum chart. These areas of the Spectrum Data section display the data for the x-axis (shown in the area labeled as Number 2) and y-axis, (shown in the area labeled as Number 3).
If the software does not read any data back, take the following steps:
If there are issues getting SNR performance, note the following:
Software compatible with CED evaluation board available here.
|AD7944||Product Page, AD7944, 14-bit, 2.5 MSPS ADC with internal reference|
|AD7985||Product Page, AD7985, 16-bit, 2.5 MSPS ADC with internal reference|
|AD7986||Product Page, AD7986, 18-bit, 2 MSPS differential input ADC with internal reference|
|AD8021||Product Page, AD8021, low noise, high speed amplifier|
|AD8032||Product Page, AD8031/32, low power, low noise amplifier|
|ADA4899-1||Product Page, ADA4899-1, low noise, high speed amplifier|
|ADR435||Product Page, ADR435, ultralow noise XFET voltage reference with current sink and source capability|
|ADP1715||Product Page, high accuracy low IQ, 500 mA, ANYCAP®, adjustable low dropout regulator|
|ADP3334||Product Page, ADP3334, 500 mA low dropout CMOS linear regulator with soft start|
|EVAL-CED1Z||Product Page, converter and evaluation development board|
|AN-931||Application Note, Understanding PulSAR ADC Support Circuitry|
|AN-932||Application Note, Power Supply Sequencing|