Wiki

This version (13 May 2013 16:18) was approved by JasonC.The Previously approved version (09 May 2012 16:10) is available.Diff

CMOS/LVDS Pinout

The CMOS/LVDS connection on DPG2 and DPG3 uses two AMP/Tyco 1469169-1 connectors, placed side-by-side, with 139.2mil spacing between the centers of the innermost pins on both connectors. The mating connector on the evaluation board side is two AMP/Tyco 1469028-1. Note that both connectors are always required.

Left Side Connector

The left connector when looking at the connection on the DPG from the evaluation board side (J17 on the DPG2, J8 on the DPG3)

Pin Name Description
A1 CLK_DCOA_P Data Clock Out from the DUT, into the DPG. Positive side of differential signal.(required)
B1 CLK_DCOA_N Data Clock Out from the DUT, into the DPG. Negative side of differential signal.(required)
A2 CLK_TXI_O_P Data Clock output from DPG, synchronous with “I” data. Positive side of differential signal.
B2 CLK_TXI_O_N Data Clock output from DPG, synchronous with “I” data. Negative side of differential signal.
A3 TXI_DATA_P15 “I” channel data bit 15.
B3 TXI_DATA_N15 “I” channel data bit 15, negative side in LVDS mode. Not used in CMOS mode.
A4 TXI_DATA_P14 “I” channel data bit 14.
B4 TXI_DATA_N14 “I” channel data bit 14, negative side in LVDS mode. Not used in CMOS mode.
A5 TXI_DATA_P13 “I” channel data bit 13.
B5 TXI_DATA_N13 “I” channel data bit 13, negative side in LVDS mode. Not used in CMOS mode.
A6 TXI_DATA_P12 “I” channel data bit 12.
B6 TXI_DATA_N12 “I” channel data bit 12, negative side in LVDS mode. Not used in CMOS mode.
A7 TXI_DATA_P11 “I” channel data bit 11.
B7 TXI_DATA_N11 “I” channel data bit 11, negative side in LVDS mode. Not used in CMOS mode.
A8 TXI_DATA_P10 “I” channel data bit 10.
B8 TXI_DATA_N10 “I” channel data bit 10, negative side in LVDS mode. Not used in CMOS mode.
A9 TXI_DATA_P9 “I” channel data bit 9.
B9 TXI_DATA_N9 “I” channel data bit 9, negative side in LVDS mode. Not used in CMOS mode.
A10 TXI_DATA_P8 “I” channel data bit 8.
B10 TXI_DATA_N8 “I” channel data bit 8, negative side in LVDS mode. Not used in CMOS mode.
BG1 GROUND Digital Ground
BG2 GROUND Digital Ground
BG3 GROUND Digital Ground
BG4 GROUND Digital Ground
BG5 GROUND Digital Ground
BG6 GROUND Digital Ground
BG7 GROUND Digital Ground
BG8 GROUND Digital Ground
BG9 GROUND Digital Ground
BG10 GROUND Digital Ground
C1 N/C No Connect (DPG2) / “Q” channel bi-directional, low-speed LVDS 1, positive side (DPG3)
D1 N/C No Connect (DPG2) / “Q” channel bi-directional, low-speed LVDS 1, negative side (DPG3)
C2 N/C No Connect (DPG2) / “Q” channel bi-directional, low-speed LVDS 0, positive side (DPG3)
D2 N/C No Connect (DPG2) / “Q” channel bi-directional, low-speed LVDS 0, negative side (DPG3)
C3 TXQ_DATA_P15 “Q” channel data bit 15.
D3 TXQ_DATA_N15 “Q” channel data bit 15, negative side in LVDS mode. Not used in CMOS mode.
C4 TXQ_DATA_P14 “Q” channel data bit 14.
D4 TXQ_DATA_N14 “Q” channel data bit 14, negative side in LVDS mode. Not used in CMOS mode.
C5 TXQ_DATA_P13 “Q” channel data bit 13.
D5 TXQ_DATA_N13 “Q” channel data bit 13, negative side in LVDS mode. Not used in CMOS mode.
C6 TXQ_DATA_P12 “Q” channel data bit 12.
D6 TXQ_DATA_N12 “Q” channel data bit 12, negative side in LVDS mode. Not used in CMOS mode.
C7 TXQ_DATA_P11 “Q” channel data bit 11.
D7 TXQ_DATA_N11 “Q” channel data bit 11, negative side in LVDS mode. Not used in CMOS mode.
C8 TXQ_DATA_P10 “Q” channel data bit 10.
D8 TXQ_DATA_N10 “Q” channel data bit 10, negative side in LVDS mode. Not used in CMOS mode.
C9 TXQ_DATA_P9 “Q” channel data bit 9.
D9 TXQ_DATA_N9 “Q” channel data bit 9, negative side in LVDS mode. Not used in CMOS mode.
C10 TXQ_DATA_P8 “Q” channel data bit 8.
D10 TXQ_DATA_N8 “Q” channel data bit 8, negative side in LVDS mode. Not used in CMOS mode.
DG1 GROUND Digital Ground
DG2 GROUND Digital Ground
DG3 GROUND Digital Ground
DG4 GROUND Digital Ground
DG5 GROUND Digital Ground
DG6 GROUND Digital Ground
DG7 GROUND Digital Ground
DG8 GROUND Digital Ground
DG9 GROUND Digital Ground
DG10 GROUND Digital Ground

Right Side Connector

The right connector when looking at the connection on the DPG from the evaluation board side (J18 on the DPG2, J10 on the DPG3)

Pin Name Description
A1 TXI_DATA_P7 “I” channel data bit 7.
B1 TXI_DATA_N7 “I” channel data bit 7, negative side in LVDS mode. Not used in CMOS mode.
A2 TXI_DATA_P6 “I” channel data bit 6.
B2 TXI_DATA_N6 “I” channel data bit 6, negative side in LVDS mode. Not used in CMOS mode.
A3 TXI_DATA_P5 “I” channel data bit 5.
B3 TXI_DATA_N5 “I” channel data bit 5, negative side in LVDS mode. Not used in CMOS mode.
A4 TXI_DATA_P4 “I” channel data bit 4.
B4 TXI_DATA_N4 “I” channel data bit 4, negative side in LVDS mode. Not used in CMOS mode.
A5 TXI_DATA_P3 “I” channel data bit 3.
B5 TXI_DATA_N3 “I” channel data bit 3, negative side in LVDS mode. Not used in CMOS mode.
A6 TXI_DATA_P2 “I” channel data bit 2.
B6 TXI_DATA_N2 “I” channel data bit 2, negative side in LVDS mode. Not used in CMOS mode.
A7 TXI_DATA_P1 “I” channel data bit 1.
B7 TXI_DATA_N1 “I” channel data bit 1, negative side in LVDS mode. Not used in CMOS mode.
A8 TXI_DATA_P0 “I” channel data bit 0.
B8 TXI_DATA_N0 “I” channel data bit 0, negative side in LVDS mode. Not used in CMOS mode.
A9 N/C No Connect (DPG2) / “I” channel bi-directional, low-speed LVDS 1, positive side (DPG3)
B9 N/C No Connect (DPG2) / “I” channel bi-directional, low-speed LVDS 1, negativeside (DPG3)
A10 N/C No Connect (DPG2) / “I” channel bi-directional, low-speed LVDS 0, positive side (DPG3)
B10 N/C No Connect (DPG2) / “I” channel bi-directional, low-speed LVDS 0, negative side (DPG3)
BG1 GROUND Digital Ground
BG2 GROUND Digital Ground
BG3 GROUND Digital Ground
BG4 GROUND Digital Ground
BG5 GROUND Digital Ground
BG6 GROUND Digital Ground
BG7 GROUND Digital Ground
BG8 GROUND Digital Ground
BG9 GROUND Digital Ground
BG10 GROUND Digital Ground
C1 TXQ_DATA_P7 “Q” channel data bit 7.
D1 TXQ_DATA_N7 “Q” channel data bit 7, negative side in LVDS mode. Not used in CMOS mode.
C2 TXQ_DATA_P6 “Q” channel data bit 6.
D2 TXQ_DATA_N6 “Q” channel data bit 6, negative side in LVDS mode. Not used in CMOS mode.
C3 TXQ_DATA_P5 “Q” channel data bit 5.
D3 TXQ_DATA_N5 “Q” channel data bit 5, negative side in LVDS mode. Not used in CMOS mode.
C4 TXQ_DATA_P4 “Q” channel data bit 4.
D4 TXQ_DATA_N4 “Q” channel data bit 4, negative side in LVDS mode. Not used in CMOS mode.
C5 TXQ_DATA_P3 “Q” channel data bit 3.
D5 TXQ_DATA_N3 “Q” channel data bit 3, negative side in LVDS mode. Not used in CMOS mode.
C6 TXQ_DATA_P2 “Q” channel data bit 2.
D6 TXQ_DATA_N2 “Q” channel data bit 2, negative side in LVDS mode. Not used in CMOS mode.
C7 TXQ_DATA_P1 “Q” channel data bit 1.
D7 TXQ_DATA_N1 “Q” channel data bit 1, negative side in LVDS mode. Not used in CMOS mode.
C8 TXQ_DATA_P0 “Q” channel data bit 0.
D8 TXQ_DATA_N0 “Q” channel data bit 0, negative side in LVDS mode. Not used in CMOS mode.
C9 CLK_TXQ_O_P Data Clock output from DPG, synchronous with “Q” data. Positive side of differential signal.
D9 CLK_TXQ_O_N Data Clock output from DPG, synchronous with “Q” data. Negative side of differential signal.
C10 CLK_DCOB_P Data Clock Out from the DUT, into the DPG. Positive side of differential signal. Must be phase and frequency locked with CLK_DCOA. (required for DPG2)
D10 CLK_DCOB_N Data Clock Out from the DUT, into the DPG. Negative side of differential signal. Must be phase and frequency locked with CLK_DCOA. (required for DPG2)
DG1 GROUND Digital Ground
DG2 GROUND Digital Ground
DG3 GROUND Digital Ground
DG4 GROUND Digital Ground
DG5 GROUND Digital Ground
DG6 GROUND Digital Ground
DG7 GROUND Digital Ground
DG8 GROUND Digital Ground
DG9 GROUND Digital Ground
DG10 GROUND Digital Ground
resources/eval/dpg/z-pack_pinout.txt · Last modified: 13 May 2013 16:18 by JasonC