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resources:eval:dpg:dpg3 [06 Feb 2014 23:24] Jason Coutermarsh Updated ordering link |
resources:eval:dpg:dpg3 [26 Jun 2014 14:42] Jason Coutermarsh [Multi-Unit Synchronization] |
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| * Trigger | * Trigger | ||
| * SMA jack for trigger input or output | * SMA jack for trigger input or output | ||
| - | * Multi-Unit Synchronization | ||
| - | * Up to four DPG3's may have their LVDS interfaces synchronized together | ||
| - | * Requires additional Synchronization Board and cabling | ||
| * Specified for operation at 25ºC only | * Specified for operation at 25ºC only | ||
| Line 69: | Line 66: | ||
| ===== Output Trigger ===== | ===== Output Trigger ===== | ||
| When set as an output, the trigger will pulse when the playback is running at the beginning of the vector. Therefore, it will pulse every time the vector is looped when in Loop mode, or only once if the unit is in Count mode. | When set as an output, the trigger will pulse when the playback is running at the beginning of the vector. Therefore, it will pulse every time the vector is looped when in Loop mode, or only once if the unit is in Count mode. | ||
| - | ====== Multi-Unit Synchronization ====== | ||
| - | With the appropriate external synchronization board and cables, up to four DPG3's can be synchronized together when in LVDS mode. One unit is designated as the master, and all units use the master's clock instead of their own. The data will then being playback from each unit on the same clock edge. | ||
| - | <WRAP important>Synchronizing multiple DPGs together does //not// guarantee that the analog waveforms coming out of the attached DAC evaluation board are synchronized. Each particular DAC may require additional synchronization circuitry to ensure that the analog outputs are synchronized.</WRAP> | ||
| - | |||
| - | //Note that the synchronization board and cables used with the DPG2 are not compatible with the DPG3// | ||
| - | |||
| - | <fs larger>**Multi-Unit Synchronization is not currently supported on the DPG3, but will be enabled by a future software update.**</fs> | ||
| ====== Connector Pinouts ====== | ====== Connector Pinouts ====== | ||
| The DGP3 has two separate connector systems for interfacing with evaluation boards. One, for CMOS and LVDS interface DACs, is backwards compatible with the [[resources:eval:dpg:dpg2|DPG2]]. The second connector is new to the DPG3, and supports high-speed serial, power, and communications. | The DGP3 has two separate connector systems for interfacing with evaluation boards. One, for CMOS and LVDS interface DACs, is backwards compatible with the [[resources:eval:dpg:dpg2|DPG2]]. The second connector is new to the DPG3, and supports high-speed serial, power, and communications. | ||
resources/eval/dpg/dpg3.txt · Last modified: 26 Jun 2014 14:42 by Jason Coutermarsh