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resources:eval:dpg:ad9739-ebz [08 Sep 2021 08:16]
Melissa Lorenz Lacanlale draft2
resources:eval:dpg:ad9739-ebz [28 Sep 2021 07:26] (current)
Melissa Lorenz Lacanlale Update to SDPH1 and ADSV7
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 =====Helpful Files:===== =====Helpful Files:=====
-    * [[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-R2-EBZ Quick Start Guide.pdf|AD9739-R2-EBZ ​Quick Start Guide]] for DPG3 users+    * Download the {{ :resources:​eval:​dpg:​ad9739-ebz_quick_start_guide.pdf |Quick ​start Guide}} and {{ :​resources:​eval:​dpg:​hsdacupdate_ad9739a_1.0.4820.29531.exe.zip |AD9739 Update}}for DPG3 users
     * Data Sheet: ​ [[adi>​static/​imported-files/​data_sheets/​AD9739.pdf|AD9739 Data Sheet]]     * Data Sheet: ​ [[adi>​static/​imported-files/​data_sheets/​AD9739.pdf|AD9739 Data Sheet]]
     * IBIS Model: [[adi>​en/​license/​ibis-models?​mediaPath=media/​en/​simulation-models/​ibis-models/​ad9739.ibs&​modelType=ibis-models|IBIS Model]]     * IBIS Model: [[adi>​en/​license/​ibis-models?​mediaPath=media/​en/​simulation-models/​ibis-models/​ad9739.ibs&​modelType=ibis-models|IBIS Model]]
-    * Schematic:[[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevA Schematic.pdf|AD9739-CMTS-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevB Schematic.pdf|AD9739-CMTS-EBZ RevB]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-EBZ RevA Schematic.pdf|AD9739-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-MIX-EBZ RevA Schematic.pdf|AD9739-MIX-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-R2-EBZ RevAB Schematic.pdf|AD9739-R2-EBZ RevAB]] +    * Schematic: ​{{ :resources:​eval:​dpg:​ad9739-cmts-ebz_reva_schematic.pdf |ad9739-cmts-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-cmts-ebz_revb_schematic.pdf |ad9739-cmts-ebz_revb}},​{{ ​:resources:​eval:​dpg:​ad9739-ebz_reva_schematic.pdf |ad9739-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-mix-ebz_reva_schematic.pdf |ad9739-mix-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-r2-ebz_revab_schematic.pdf |ad9739-r2-ebz_revab}} 
-    * Bill of Materials: ​[[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevA BOM_customer.xls|AD9739-CMTS-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevB BOM_customer.xls|AD9739-CMTS-EBZ RevB]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-EBZ RevA BOM_customer.xls|AD9739-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-MIX-EBZ RevA BOM_customer.xls|AD9739-MIX-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-R2-EBZ RevAB BOM_customer.xls|AD9739-R2-EBZ RevAB]] +    * Bill of Materials: ​{{ :resources:​eval:​dpg:​ad9739-cmts-ebz_reva_bom_customer.xls |ad9739-cmts-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-cmts-ebz_revb_bom_customer.xls |ad9739-cmts-ebz_revb}}, {{ :resources:​eval:​dpg:​ad9739-ebz_reva_bom_customer.xls |ad9739-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-mix-ebz_reva_bom_customer.xls |ad9739-mix-ebz_reva}},​{{ ​:resources:​eval:​dpg:​ad9739-r2-ebz_revab_bom_customer.xls |ad9739-r2-ebz_revab}} 
-    * PCB Gerber files: ​[[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevA Gerber Files.zip|AD9739-CMTS-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevB Gerber Files.zip|AD9739-CMTS-EBZ RevB]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-EBZ RevA Gerber Files.zip|AD9739-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-MIX-EBZ RevA Gerber Files.zip|AD9739-MIX-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-R2-EBZ RevAB Gerber Files.zip|AD9739-R2-EBZ RevAB]]+ 
 + 
 +    * PCB Gerber files: ​{{ :resources:​eval:​dpg:​ad9739-cmts-ebz_reva_gerber_files.zip |ad9739-cmts-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-cmts-ebz_revb_gerber_files.zip |ad9739-cmts-ebz_revb}}, {{ :resources:eval:​dpg:​ad9739-ebz_reva_gerber_files.zip |ad9739-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-r2-ebz_revab_gerber_files.zip |ad9739-r2-ebz_revab}} 
     * PCB BRD file: [[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevA.brd|AD9739-CMTS-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevB.brd|AD9739-CMTS-EBZ RevB]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-EBZ RevA.brd|AD9739-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-MIX-EBZ RevA.brd|AD9739-MIX-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-R2-EBZ RevAB.brd|AD9739-R2-EBZ RevAB]]     * PCB BRD file: [[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevA.brd|AD9739-CMTS-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevB.brd|AD9739-CMTS-EBZ RevB]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-EBZ RevA.brd|AD9739-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-MIX-EBZ RevA.brd|AD9739-MIX-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-R2-EBZ RevAB.brd|AD9739-R2-EBZ RevAB]]
-    * PCB Layout PDF: [[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevA Layout.pdf|AD9739-CMTS-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-CMTS-EBZ RevB Layout.pdf|AD9739-CMTS-EBZ RevB]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-EBZ RevA Layout.pdf|AD9739-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-MIX-EBZ RevA Layout.pdf|AD9739-MIX-EBZ RevA]][[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​Documents/​AD9739/​AD9739-R2-EBZ RevAB Layout.pdf|AD9739-R2-EBZ RevAB]] +    ​ 
- +    ​* PCB Layout PDF: {{ :resources:​eval:​dpg:​ad9739-cmts-ebz_reva_layout.pdf |ad9739-cmts-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-cmts-ebz_revb_layout.pdf |ad9739-cmts-ebz_revb}}, {{ :resources:eval:​dpg:​ad9739-ebz_reva_layout.pdf  |ad9739-ebz_reva}}, {{ :resources:​eval:​dpg:​ad9739-r2-ebz_revab_gerber_files.zip |ad9739-r2-ebz_revab}}
-Download the [[ftp://​ftp.analog.com/​pub/​HSSP_SW/​HSCDAC/​HSDAC_Update/​HSDACUpdate_AD9739_1.0.4686.25994.exe|AD9739 Update]]+
  
 =====Software Needed:​===== =====Software Needed:​=====
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 =====Hardware Needed:​===== =====Hardware Needed:​=====
-  * [[adi>​eval-ad9146|AD9146-M5375-EBZ]] Evaluation Board+  * [[adi>​eval-ad9739|AD9739-R2-EBZ]] Evaluation Board
   * [[:​resources:​eval:​dpg:​hsdac-sdp-h1|SDP-H1]] (EVAL-SDP-CH1Z) or [[:​resources:​eval:​ads7-v2|ADS7-V2EBZ]] ​   * [[:​resources:​eval:​dpg:​hsdac-sdp-h1|SDP-H1]] (EVAL-SDP-CH1Z) or [[:​resources:​eval:​ads7-v2|ADS7-V2EBZ]] ​
-  * Evaluation Kit 
   * [[adi>​AD-DAC-FMC]]-ADP High-Speed DAC Evaluation Board to FMC Adaptor Board   * [[adi>​AD-DAC-FMC]]-ADP High-Speed DAC Evaluation Board to FMC Adaptor Board
   * 5Vdc 2A Power Supply   * 5Vdc 2A Power Supply
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   * USB-A to USB-Mini Cable   * USB-A to USB-Mini Cable
   * (2) SMA Cables   * (2) SMA Cables
-  ​<fc #ff0000>* Power supply ​to SMA connector</​fc>​+  * Power Supply ​to SMA cable
   * The following are included in SDP-H1 Evaluation Kit:   * The following are included in SDP-H1 Evaluation Kit:
     * 12Vdc 2.5A Wall Wart     * 12Vdc 2.5A Wall Wart
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 =====Quick Start Guide===== =====Quick Start Guide=====
- - Attach the evaluation board to the FMC connector of SDP-H1 or ADS7-V2 using the AD-DAC-FMC-ADP adapter board. Connect continuous wave generator for clock input to J1, and the DAC output from J5 or J9 to a signal/​spectrum analyzer. Connect the evaluation board to PC via USB and to a 5Vdc 2A power supply ​via banana plug cables. Refer to Figures 1a and 1b.+  ​- Attach the evaluation board to the FMC connector of SDP-H1 or ADS7-V2 using the AD-DAC-FMC-ADP adapter board. Connect continuous wave generator for clock input to J3, and the DAC output from J1 to a signal/​spectrum analyzer. Connect the evaluation board to PC via USBa 5Vdc 2A power supply ​to J17. Refer to Figures 1a and 1b.
      * If using **SDP-H1**, set clock input to **300 MHz and 0 dBm**. Connect SDP-H1 to PC via USB and to a 12Vdc wall wart.      * If using **SDP-H1**, set clock input to **300 MHz and 0 dBm**. Connect SDP-H1 to PC via USB and to a 12Vdc wall wart.
      * If using **ADS7-V2**,​ set the clock input to **2 GHz and 0 dBm**. Connect ADS-V2 to PC via USB and to a 12V 60W AC/DC power supply. Switch the board ON using S1 beside the connector for 12V supply.      * If using **ADS7-V2**,​ set the clock input to **2 GHz and 0 dBm**. Connect ADS-V2 to PC via USB and to a 12V 60W AC/DC power supply. Switch the board ON using S1 beside the connector for 12V supply.
-  - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9146 ​evaluation board. ​Apply the configuration wizard settings shown in Figure 2a for SDP-H1 ​and in Figure 2b for ADS7-V2. <WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9146_ace_sdp-h1.png?600 }}//Figure 2a. ACE Initial Configuration Wizard ​when using SDP-H1//</​WRAP><​WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9146_ace_ads7-v2.png?600 }}//​Figure ​2b. ACE Initial Configuration Wizard ​when using ADS7-V2//</​WRAP>​ +  - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9739 ​evaluation board. ​From the AD9739-EBZ tab, Click **“Run Example Startup Routine (Sync Disabled)”**.  
-     * If using **SDP-H1**, ​set **DAC frequency** to 100 MHz, **Interpolation** to 2x and **Data Format** to binary format+     * If using **SDP-H1**, The MU Controller Locked indicator should light up as shown in figure 2a. 
-     * If using **ADS7-V2**, ​set **DAC frequency** to 500 MHz, **Interpolation** to 2x and **Data Format** to binary format. +     * If using **ADS7-V2**, The first three indicators should light up as shown in figure 2b. <WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9739_ace_boardview.png?nolink&600 |}}//Figure 2a. ACE Initial ​Board Configuration Wizard ​for SDP-H1//</​WRAP>​ <WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9739_ads7_ace_boardview.png?nolink&600 |}}//​Figure ​2a. ACE Initial ​Board Configuration Wizard ​for ADS7-V2//</​WRAP>​ 
- +  - Double click the AD9739 Box to open chip view.  
- +     * If using **SDP-H1**, ​The DLL_LOCKED indicator should light up as shown in figure 3a
- +     * If using **ADS7-V2**, ​All three indicators ​should ​light up as shown in figure 3b. <WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9739_ace_chipview.png?nolink&​600 ​|}}//Figure 3a. ACE Initial ​Board Configuration Wizard for SDP-H1//</WRAP> <​WRAP ​centeralign>{{ :​resources:​eval:​dpg:​ad9739_adsv7_ace_chipview.png?nolink&​600 ​|{{ :​resources:​eval:​dpg:​ad9739_ads7_ace_boardview.png?nolink&​600 |}}//Figure 3bACE Initial Board Configuration Wizard for ADS7-V2//</​WRAP>​ 
-===== Getting Started with the AD9739A Evaluation Board ===== +  Start DPG Lite or DPG Downloader
-==== What's in the Box ==== +    * At the SDP-H1 settingsensure that Evaluation board is equal to AD9739 ​and **DCO frequency** ​of around **75 MHz** should be displayed. 
-  * AD9739-R2-EBZ Evaluation Board  +    * At the ADS7-V2 settingsensure ​that Evaluation board is equal to AD9739 and **DCO frequency** ​of around **500 MHz** should be displayed. 
-  * Mini-USB Cable  +  - In DPG Lite or DPG Downloaderfrom the **Add Generator Waveforms** pulldown menuselect **Single Tone** ​and apply the settings ​as shown in Figures 4a and 4b.  
-  * AD9739 Evaluation Board CD +    * When using SDP-H1set **Data Rate** to 300 MHz and **Desired ​Frequency** to 20 MHz
-==== Recommended Equipment ==== +    * When using ADS-V2set **Data Rate** to 2 GHz and **Desired Frequency** ​to 180 MHz. 
-  * Digital Pattern Generator (DPG2): ADI HSC-DAC-DPG-BZ  +  - Continuing on setting up DPG Lite or DPG Downloader, set **DAC resolution** to 14 bits. Check off the **Unsigned Data** box. 
-  * +5Vdc Power Supply Ex: Agilent E3630A +  - Select ​the Single Tone from the **Data Vector** pulldown menu \\ <WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9739_dpg_sdph1.png?nolink&​600 |}}//Figure 4aDPG Lite session for SDP-H1//</​WRAP><​WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9739_dpg-lite_ads7-v2.png?nolink&​600 ​|}}//Figure 4bDPG Lite session for ADS7-V2//</​WRAP>​ 
-  * Low Phase Noise Clock Source or ADF4350 Evaluation Board +  - Press the download arrow and then the play button. The FFT plots similar ​to Figures 5a and 5b should ​appear in the signal/spectrum analyzer.\\ <WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9739_fout_sdp-h1.png?nolink&600 |}}//Figure 5aEVAL-AD9739 ​FFT for Data Rate = 300 MHzFout 20 MHz using SDP-H1//</​WRAP><​WRAP centeralign>​{{ :​resources:​eval:​dpg:​ad9739_fout_ads7.png?nolink&​600 |}}//Figure 5bEVAL-AD9739 FFT for Data Rate 2 GHzFout 180 MHz using AD7-V2//</​WRAP>​
-  * Spectrum Analyzer Ex: Agilent PSA or Rohde & Schwarz FSU  +
-  * PC: Windows PC with 2 or more USB ports +
-==== Introduction ==== +
-The AD9739 Evaluation Board connects to the Analog Devices Digital Pattern Generator (DPG2) to allow for quick evaluation of the AD9739. The DPG2 allows the user to create many types of digital vectors and transmit these at speed to the AD9739 in any of the AD9739 operating modes. The AD9739 evaluation board is configured over USB with accompanying PC software. +
-==== Software Installation ==== +
-The DAC Software Suite plus AD9739 Update ​should ​be installed on the PC prior connecting the hardware to the PC. The DAC Software Suite is included on the Evaluation Board CD, or can be downloaded from the DPG web site at http://​www.analog.com/​dpg. This will install DPGDownloader (for loading vectors into the DPG2) and the AD9739 SPI Controller application. +
-==== Hardware Setup ==== +
-To operate the board, a power supply capable of +5vdc, 2A should be connected to J17. A spectrum analyzer or an oscilloscope to view the DAC output should be connected to J1/J2 (See Figure 1). The diagram ​in Figure 1shows the location of each connectionA low jitter (0.5psec RMS) sine or square wave clock source should be connected to J3. The DC level of the clock is unimportant since the clock is AC-coupled on the evaluation board before the CLKP/N inputs. The included USB cable should be used to connect the Evaluation Board to a PC. +
-{{ :​resources:​eval:​dpg:​9739_hardware_revisions.png?550 |}} +
-==== Evaluation ​Board Editions ==== +
-The AD9739 Evaluation Board has four versions: “Normal” (AD9739-EBZ), “Mix Mode” (AD9739-MIX-EBZ),​ and “CMTS” (AD9739-CMTS-EBZ) and the newer AD9739-R2-EBZ.  +
-<​WRAP ​important>The three previous evaluation boards are now obsolete, and have all been replaced by the AD9739-R2-EBZ. References to the older evaluation boards remain in the documentation for users with the older boards.  +
-The four editions differ only in the output stage configuration. The software used to evaluate all four boards is identical.</WRAP> +
-=== R2 === +
-The new R2 board is designed to allow evaluation of the AD9739 over the entire operating range. It uses a TC1-33-75G2+ balun transformer,​ as shown below. +
-{{ :​resources:​eval:​dpg:​9739_r2.png? |}} +
-=== Normal === +
-In normal mode, there is no filter and the only components are the 90Ω resistors to terminate the DAC outputs and the two transformers (balun and center tap) as shown below. +
-{{ :​resources:​eval:​dpg:​9739_normal.png?:650 }} +
-=== Mix-Mode === +
-The Mix-Mode configuration is targeted at applications using the 2nd and 3rd Nyquist zones using the analog mix modeIn this application,​ the ETC1-1-13 balun transformer is used as shown below. +
-{{ :​resources:​eval:​dpg:​9739_mix-mode.png?:650 }} +
-=== CMTS === +
-This configuration was for applications targeting cable infrastructure applications up to 1GSPS. In this configuration,​ a JTX-2-10T transformer is usedwhich is effectively a balun and center-tap transformer in one package. A filter network is used to help balance the impedance between the DAC and transformer,​ and helps to knock down some of the images in the 2nd Nyquist zoneThese images would otherwise end up folding back into the desired 1GHz bandwidth (depending on the location of the desired carriers). ​ The output configuration for this application is shown below. +
-{{ :​resources:​eval:​dpg:​9739_cmts.png?​650 |}} +
-===== Getting Started ===== +
-This quick-start will setup a single-tone output from the AD9739 to provide a brief introduction to the partas well as a basic functionality test. Note that while this is a valid setup on all three versions ​of the board, it should ​not be used for performance measurementsFor performance testing, ensure that  an appropriate vector and frequency plan is used with the correct board version. To beginopen the AD9739 SPI application (Start > Programs > Analog Devices > AD9739-EBZ > AD9739 SPI). Connect a +5Vdc power supply to J17, and connect a 2GHz, 0dBm clock to J3. +
-==== Enable Mu Controller ==== +
-In order to optimize and lock the Mu Controller, it is only necessary to have the DAC clock running (no data needs to be presented). Click the MU_ENA button in the MU Controller section of the SPI controller, ​as shown in Figure 5. Then run the SPI controller by clicking on the Run button ({{:​resources:​eval:​dpg:​image004.png?​|}}) in the upper left of the screen+
-{{ :​resources:​eval:​dpg:​mu_controller_9739.png?:​900 }} +
-==== Generating a Test Vector ==== +
-Open DPGDownloader (Start > Programs > Analog Devices > DPG > DPGDownloader). Ensure that “AD9739” is selected in the Evaluation Board drop-down list. For this evaluation board, “LVDS” is the only valid Port Configuration, and will be selected automatically. The Data Clock Frequency ​display should read approximately 500MHz+
-Click on Add Generated Waveform, and then Single Tone, as shown below. A Single Tone panel will be added to the vector listStart by entering the Clock Frequency (2GHz in this case). You can enter 2G in the box. Nextenter 200MHz (200M) as the desired frequency of the tone. The DAC Resolution should be set at 14 bits. Next, in the lower portion of the screen, select “1: Single Tone” as the Data Vector. The other options can be left at their default. +
-{{ :​resources:​eval:​dpg:​9739_dpgdownloader.png? }} +
-After the DPG2 is correctly setup, click the Download button ({{:​resources:​eval:​dpg:​dpgdownloader_downloadvector.png?|}}) in the lower right, then the Play button ({{:​resources:​eval:​dpg:​dpgdownloader_startresume.png?|}}) to begin vector playback into the AD9739+
-==== Enable LVDS Controller ==== +
-Once the pattern is loaded into the DPG2 and running, ​the final step is to enable the LVDS Controller. In the AD9739 SPI controller, enable the RCV_LOOP and RCV_ENA buttons. Click the Run button ​({{:​resources:​eval:​dpg:​image004.png?​}}). Once the run is complete, the RCVR LCK and RCVR TRX ON indicators should be green, as shown below. +
-{{:​resources:​eval:​dpg:​lvds_9739.png?:​900}} +
- +
-{{ :​resources:​eval:​dpg:​dci_9739.png?​}}Another way to verify that the controller is in the correct spot (and not on the edge) is to check the status of the four status bits which sample the rising edge of the DCI at four different phases. DCI PHS1 should always be high, and DCI PHS3 should always be low. The other bits will toggle as the LVDS controller searches for the correct timing. The ideal case is shown to the right Increasing the value of the FINE_DEL_SKEW allows for a wider search around the DCI edge, and should ​reduce ​the toggling on PHS0 and PHS2. This is usually required when the DCI signal ​has a lot of jitter. +
-==== Result ==== +
-The final result of this setup should be as shown below. +
-{{ :​resources:​eval:​dpg:​results_9739.png?:600 }} +
-===== SPI Controller ===== +
-The SPI controller software is broken up into numerous sections. Several of them are described here, as they pertain to the evaluation board. For complete descriptions of each SPI register, see the AD9739 datasheet. In the interest of continuous quality improvements,​ the images below may not exactly match your version of the software. +
-==== SPI Settings and Powerdown/Reset ==== +
-{{ :​resources:​eval:​dpg:​9739_powerdown.png?:​150}} +
-These bits (shown to the right) control the operation of the SPI port on the AD9739, as well as the master reset and individual power-down bits. Changing the SDIO DIR or DATADIR bits will cause the SPI controller application to stop functioning correctly. Do not change these bits. The Reset button is “sticky”,​ that is, the part will stay in reset for as long as the button is enabled. To reset the partset this bit, run the SPI controller, then unset this bit and run the controller again. +
-==== Controller Clock Controls and Analog FS controls ==== +
-{{ :​resources:​eval:​dpg:​9739_controller_clock.png?:250}} +
-The Controller Clock controls enable the Mu Controller and LVDS controllersFor normal operation, both of these should be enabled. The Clock GEN PD switch powers down the clocking structure, and should be left disabled for normal use. The DAC current ouput has an adjustable full-scale value. The FSC Setoption allows ​for this adjustment.  +
-After running the SPI controller, the full-scale current in miliamps will be displayed here. +
-  * Mu Controller Clock Enable: Register 0x02 Bit 0 +
-  * LVDS Controller Clock Enable: Register 0x02 Bit 1 +
-  * Analog Full-Scale Setting (10 bit Gain DAC 10-30mA adjustment):​ Register 0x06 bit 0:8, Register 0x07 bits 0,1 +
-==== Decoder Controller and IRQ Controls ==== +
-{{ :​resources:​eval:​dpg:​9739_decoder_controller.png?​300|}} +
-^Decoder Mode:^ Register 0x08 Bits 0,1 ^ +
-|Normal|0x0| +
-|Return to zero|0x1| +
-|Mix Mode|0x2| +
-==== Cross Control ==== +
-{{ :​resources:​eval:​dpg:​9739_cross_control.png?​200|}} +
-  * CLKP Offset Setting: Register 0x24 Bits 0-3  +
-  * CLKP Direction Bit: Register 0x24 Bit 4  +
-  * CLKP Offset Setting: Register 0x25 Bits 0-3  +
-  * CLKP Direction Bit: Register 0x25 Bit 4  +
-  * Damp: Register 0x25 Bits 7 +
-==== Mu Controller ==== +
-  * Enable: Register 0x26 Bit 0 (Set to 1 to enable the controller)  +
-  * Mu Controller Gain: Register 0x26 Bits 1,2 (Optimal Setting is a Gain of 1)  +
-  * MU Desired Phase: Desired Phase Value for Phase to Voltage Converter to Optimize Mu Controller. The  +
-optimal setting is negative 6 (max of 16) . Register 0x27 bits 0-4  +
-  * Slope: Slope the mu contoller will lock onto Register 0x26 bit 6 (Optimal setting is Negative slope set bit to 0)  +
-  * MU_DEL_Manual:​ Register 0x28 bits 0-7 and 0x27 bits 6,7: Sets the point where the Mu Controller begins to  +
-search. It is best to set it to the middle of the delay line . The maximum Mu delay is 432, so set these bits to  +
-approximately 220. +
- +
-Sets the Mode in which the Controller searches: +
-^Mode^ Register: 0x26 Bits 4, 5^ +
-|Search and Track (Optimal Setting)| 0x00| +
-|Track Only| 0x01| +
-|Search Only| 0x10| +
-|Invalid| 0x11| +
- +
-Sets the Mode in which the search for the optimal phase is performed:​ +
-^Search Mode^ Register: 0x27 – Bits 5, 6^ +
-|Down| 0x00| +
-|Up| 0x01| +
-|Up/Down (Optimal Setting)| 0x10| +
-|Invalid| 0x11|  +
-Search GB: sets a GB from the beginning and end of the Mu Delay line in which the Mu controller will not enter  +
-into unless it does not find a valid phase outside the GB. Register 0x29 bits 0-4. Optimal value is Decimal 11. +
-  +
-Tolerance: Sets the Tolerance of the phase search. Register 0x29 bit 7 +
-  * 0 – Not Exact. Can find a phase within 2 phases of the desired phase  +
-  * 1- Exact. Finds the exact phase you are targeting (Optimal Setting) +
- +
-ContRST: Controls whether the controller will reset or continue if it does not find the desired phase  +
-  * 0 – Continue (Optimal Setting)  +
-  * 1 – Reset +
- +
-Phase Detector Enable: Register 0x24 bit 5. Enables the Phase Detector (Set to 1 to enable the Phase Detector)  +
- +
-Phase Detector Comparator Boost: Optimizes the bias to the Phase Detector (Set to 1 to enable)  +
- +
-Bias: Register 0x24 Bits 0-3: Manual Control of the bias if the Boost control is not enabled  +
- +
-Duty Cycle Fix: Register 0x25 Bit 7 Enables the duty cycle correction in the Mu Controller. Recommended to  +
-always enable (Set to 1 to enable)+
  
-Direction: Register 0x25 Bit 6 Sets the direction that the duty cycle will be corrected ​ 
-  * 0 – Negative (Optimal Setting) ​ 
-  * 1 - Positive 
  
-OffsetRegister Register 0x25 Bit 0-5 Sets the Duty Cycle Correction manually ​if Fix is not enabled+=====Troubleshooting===== 
 +This section lists items to check and practices to use when debugging any unexpected performance of a board. If unexpected results occur: 
 +  * Check if the Voltage supply test points of the evaluation board has the correct value.  
 +  * Check if all (3) blue LEDs on the AD-DAC-FMC-ADP board is lit up. Reconnect ​the board to the FMC connector of SDP-H1 ​if not lit up. 
 +  * Check if the SDP-H1 ​is being supplied properly by 12Vdc adaptor. Some LEDs on the SDP-H1 should lit up. 
 +  * Power cycle both the SDP-H1/​ADS7-V2 and the AD9739 evaluation board. 
 +  * Check on the Spectrum Analyzer if the DAC clock inputs are properly driven. For 300MHz clock using SDP-H1, the spectrum analyzer should detect a weak signal at 300MHz. For 2GHz clock using ADS7-V2, the spectrum analyzer should detect a weak signal at 2GHz.  If not detected, check properly the clock source and connections. 
 +  * Disconnect and reconnect the SDP-H1 /ADS7-V2 and AD9739 evaluation board. Reopen DPG Lite software.
  
-The status read back bits for the mu controller are as follows: ​ 
-  * MU_LCK: Register 0x2A bit 0 (value of 1 means the controller is locked) 
-  * LST_LCK: Register 0x2A bit 1 (Value of 1 means the control lost lock) 
-In order to read back the present MU Delay and phase value, it is necessary to set the Read bit high and then  
-low before the values can be read back: 
-  * Read: Register 0x26 Bit 3  
-  * Mu Delay Readback: Register 0x28 bits 0-7 and 0x27 bits 6,7  
-  * (Total of 9 bits in the read back the maximum Mu delay value is d432 or x1B0)  
-  * MUD_PH_Readback:​ Register 0x27 bits 0-4 – Phase the controller locked to. 
-In order to use the Mu controller in manual mode the following bits are utilized: ​ 
-  * Mu Controller Enable: Register 0x26 Bit 0 (Set to 0 to disable the controller) ​ 
-  * MU_DEL_Manual:​ Register 0x28 bits 0-7 and 0x27 bits 7,8. (Total of 9 bits the maximum Mu delay value is d432 or x1B0) 
-==== LVDS Receiver Controls ==== 
-  * RCV_LOOP - On (Register 0x10 bit 1 set to 1) 
-  * RCV_ENA - On (Register 0x10 bit 0 set to 1)  
-  * LCKTHR - 2 (Register 0x15 bits 0-4)  
-  * RVCR_GAIN - 1 (Register 0x11 bit 0 set to 1)  
-  * FINE_DELAY_MID - 7 (Register 0x11 bits 2-5)  
-  * FINE_DELAY_SKEW - 2 (Register 0x13 bits 0-4)  
-  * Sample_Delay:​ Sets the midpoint where the controller begins to search Register 0x11 bits 6,7  
-Register 0x12 Optimal value is 166 which is the center of the delay line. The maximum delay value is d333 or x14D.  
-  * DCI_Delay: Must be equal to the Sample_delay. Register 0x13 bits 4-7 Register 0x14 bits 0-5. Optimal value is also 166 which is the center of the delay line. The maximum delay value is d333 or x14D. 
-To ensure that the LVDS Controller is locked and tracking check the status of the following bits:  
-  * RCVR Lock (Register 0x21 bit 0) This should be high if the controller is locked ​ 
-  * TRK_ON (Register 0x21 bit 3) This should be high if the controller is tracking 
resources/eval/dpg/ad9739-ebz.1631081816.txt.gz · Last modified: 08 Sep 2021 08:16 by Melissa Lorenz Lacanlale