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| resources:eval:dpg:ad9739-ebz [08 Sep 2021 08:16] – draft2 Melissa Lorenz Lacanlale | resources:eval:dpg:ad9739-ebz [28 Sep 2021 07:26] – Update to SDPH1 and ADSV7 Melissa Lorenz Lacanlale | ||
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| =====Helpful Files:===== | =====Helpful Files:===== | ||
| - | * [[ftp:// | + | * Download the {{ :resources: |
| * Data Sheet: | * Data Sheet: | ||
| * IBIS Model: [[adi> | * IBIS Model: [[adi> | ||
| - | * Schematic:[[ftp:// | + | * Schematic: |
| - | * Bill of Materials: | + | * Bill of Materials: |
| - | * PCB Gerber files: | + | |
| + | |||
| + | * PCB Gerber files: | ||
| * PCB BRD file: [[ftp:// | * PCB BRD file: [[ftp:// | ||
| - | * PCB Layout PDF: [[ftp:// | + | |
| - | + | | |
| - | Download the [[ftp:// | + | |
| =====Software Needed: | =====Software Needed: | ||
| Line 34: | Line 36: | ||
| =====Hardware Needed: | =====Hardware Needed: | ||
| - | * [[adi> | + | * [[adi> |
| * [[: | * [[: | ||
| - | * Evaluation Kit | ||
| * [[adi> | * [[adi> | ||
| * 5Vdc 2A Power Supply | * 5Vdc 2A Power Supply | ||
| Line 44: | Line 45: | ||
| * USB-A to USB-Mini Cable | * USB-A to USB-Mini Cable | ||
| * (2) SMA Cables | * (2) SMA Cables | ||
| - | | + | * Power Supply |
| * The following are included in SDP-H1 Evaluation Kit: | * The following are included in SDP-H1 Evaluation Kit: | ||
| * 12Vdc 2.5A Wall Wart | * 12Vdc 2.5A Wall Wart | ||
| Line 54: | Line 55: | ||
| =====Quick Start Guide===== | =====Quick Start Guide===== | ||
| - | - Attach the evaluation board to the FMC connector of SDP-H1 or ADS7-V2 using the AD-DAC-FMC-ADP adapter board. Connect continuous wave generator for clock input to J1, and the DAC output from J5 or J9 to a signal/ | + | |
| * If using **SDP-H1**, set clock input to **300 MHz and 0 dBm**. Connect SDP-H1 to PC via USB and to a 12Vdc wall wart. | * If using **SDP-H1**, set clock input to **300 MHz and 0 dBm**. Connect SDP-H1 to PC via USB and to a 12Vdc wall wart. | ||
| * If using **ADS7-V2**, | * If using **ADS7-V2**, | ||
| - | - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9146 | + | - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9739 |
| - | * If using **SDP-H1**, | + | * If using **SDP-H1**, The MU Controller Locked indicator should light up as shown in figure 2a. |
| - | * If using **ADS7-V2**, | + | * If using **ADS7-V2**, The first three indicators should light up as shown in figure 2b. <WRAP centeralign> |
| - | + | - Double click the AD9739 Box to open chip view. | |
| - | + | * If using **SDP-H1**, | |
| - | + | * If using **ADS7-V2**, | |
| - | ===== Getting Started with the AD9739A Evaluation Board ===== | + | - Start DPG Lite or DPG Downloader. |
| - | ==== What's in the Box ==== | + | * At the SDP-H1 settings, ensure that Evaluation board is equal to AD9739 |
| - | * AD9739-R2-EBZ Evaluation Board | + | * At the ADS7-V2 settings, ensure |
| - | * Mini-USB Cable | + | - In DPG Lite or DPG Downloader, from the **Add Generator Waveforms** pulldown menu, select **Single Tone** |
| - | * AD9739 Evaluation Board CD | + | * When using SDP-H1, set **Data Rate** to 300 MHz and **Desired |
| - | ==== Recommended Equipment ==== | + | * When using ADS-V2, set **Data Rate** to 2 GHz and **Desired Frequency** |
| - | * Digital Pattern Generator (DPG2): ADI HSC-DAC-DPG-BZ | + | - Continuing on setting up DPG Lite or DPG Downloader, set **DAC resolution** to 14 bits. Check off the **Unsigned Data** box. |
| - | * +5Vdc Power Supply Ex: Agilent E3630A | + | - Select |
| - | * Low Phase Noise Clock Source or ADF4350 Evaluation Board | + | - Press the download arrow and then the play button. The FFT plots similar |
| - | * Spectrum Analyzer Ex: Agilent PSA or Rohde & Schwarz FSU | + | |
| - | * PC: Windows PC with 2 or more USB ports | + | |
| - | ==== Introduction ==== | + | |
| - | The AD9739 Evaluation Board connects to the Analog Devices Digital Pattern Generator (DPG2) to allow for quick evaluation of the AD9739. The DPG2 allows the user to create many types of digital vectors and transmit these at speed to the AD9739 in any of the AD9739 operating modes. The AD9739 evaluation board is configured over USB with accompanying PC software. | + | |
| - | ==== Software Installation ==== | + | |
| - | The DAC Software Suite plus AD9739 Update | + | |
| - | ==== Hardware Setup ==== | + | |
| - | To operate the board, a power supply capable of +5vdc, 2A should be connected to J17. A spectrum analyzer or an oscilloscope to view the DAC output should be connected to J1/J2 (See Figure 1). The diagram | + | |
| - | {{ : | + | |
| - | ==== Evaluation | + | |
| - | The AD9739 Evaluation Board has four versions: “Normal” (AD9739-EBZ), “Mix Mode” (AD9739-MIX-EBZ), | + | |
| - | < | + | |
| - | The four editions differ only in the output stage configuration. The software used to evaluate all four boards is identical.</WRAP> | + | |
| - | === R2 === | + | |
| - | The new R2 board is designed to allow evaluation of the AD9739 over the entire operating range. It uses a TC1-33-75G2+ balun transformer, | + | |
| - | {{ : | + | |
| - | === Normal === | + | |
| - | In normal mode, there is no filter and the only components are the 90Ω resistors to terminate the DAC outputs and the two transformers (balun and center tap) as shown below. | + | |
| - | {{ : | + | |
| - | === Mix-Mode === | + | |
| - | The Mix-Mode configuration is targeted at applications using the 2nd and 3rd Nyquist zones using the analog mix mode. In this application, | + | |
| - | {{ : | + | |
| - | === CMTS === | + | |
| - | This configuration was for applications targeting cable infrastructure applications up to 1GSPS. In this configuration, | + | |
| - | {{ : | + | |
| - | ===== Getting Started ===== | + | |
| - | This quick-start will setup a single-tone output from the AD9739 to provide a brief introduction to the part, as well as a basic functionality test. Note that while this is a valid setup on all three versions | + | |
| - | ==== Enable Mu Controller ==== | + | |
| - | In order to optimize and lock the Mu Controller, it is only necessary to have the DAC clock running (no data needs to be presented). Click the MU_ENA button in the MU Controller section of the SPI controller, | + | |
| - | {{ : | + | |
| - | ==== Generating a Test Vector ==== | + | |
| - | Open DPGDownloader (Start > Programs > Analog Devices > DPG > DPGDownloader). Ensure that “AD9739” is selected in the Evaluation Board drop-down list. For this evaluation board, “LVDS” is the only valid Port Configuration, and will be selected automatically. The Data Clock Frequency | + | |
| - | Click on Add Generated Waveform, and then Single Tone, as shown below. A Single Tone panel will be added to the vector list. Start by entering the Clock Frequency (2GHz in this case). You can enter 2G in the box. Next, enter 200MHz (200M) as the desired frequency of the tone. The DAC Resolution should be set at 14 bits. Next, in the lower portion of the screen, select “1: Single Tone” as the Data Vector. The other options can be left at their default. | + | |
| - | {{ : | + | |
| - | After the DPG2 is correctly setup, click the Download button ({{: | + | |
| - | ==== Enable LVDS Controller ==== | + | |
| - | Once the pattern is loaded into the DPG2 and running, | + | |
| - | {{: | + | |
| - | + | ||
| - | {{ : | + | |
| - | ==== Result ==== | + | |
| - | The final result of this setup should be as shown below. | + | |
| - | {{ : | + | |
| - | ===== SPI Controller ===== | + | |
| - | The SPI controller software is broken up into numerous sections. Several of them are described here, as they pertain to the evaluation board. For complete descriptions of each SPI register, see the AD9739 datasheet. In the interest of continuous quality improvements, | + | |
| - | ==== SPI Settings and Powerdown/Reset ==== | + | |
| - | {{ : | + | |
| - | These bits (shown to the right) control the operation of the SPI port on the AD9739, as well as the master reset and individual power-down bits. Changing the SDIO DIR or DATADIR bits will cause the SPI controller application to stop functioning correctly. Do not change these bits. The Reset button is “sticky”, | + | |
| - | ==== Controller Clock Controls and Analog FS controls ==== | + | |
| - | {{ : | + | |
| - | The Controller Clock controls enable the Mu Controller and LVDS controllers. For normal operation, both of these should be enabled. The Clock GEN PD switch powers down the clocking structure, and should be left disabled for normal use. The DAC current ouput has an adjustable full-scale value. The FSC Setoption allows | + | |
| - | After running the SPI controller, the full-scale current in miliamps will be displayed here. | + | |
| - | * Mu Controller Clock Enable: Register 0x02 Bit 0 | + | |
| - | * LVDS Controller Clock Enable: Register 0x02 Bit 1 | + | |
| - | * Analog Full-Scale Setting (10 bit Gain DAC 10-30mA adjustment): | + | |
| - | ==== Decoder Controller and IRQ Controls ==== | + | |
| - | {{ : | + | |
| - | ^Decoder Mode:^ Register 0x08 Bits 0,1 ^ | + | |
| - | |Normal|0x0| | + | |
| - | |Return to zero|0x1| | + | |
| - | |Mix Mode|0x2| | + | |
| - | ==== Cross Control ==== | + | |
| - | {{ : | + | |
| - | * CLKP Offset Setting: Register 0x24 Bits 0-3 | + | |
| - | * CLKP Direction Bit: Register 0x24 Bit 4 | + | |
| - | * CLKP Offset Setting: Register 0x25 Bits 0-3 | + | |
| - | * CLKP Direction Bit: Register 0x25 Bit 4 | + | |
| - | * Damp: Register 0x25 Bits 7 | + | |
| - | ==== Mu Controller ==== | + | |
| - | * Enable: Register 0x26 Bit 0 (Set to 1 to enable the controller) | + | |
| - | * Mu Controller Gain: Register 0x26 Bits 1,2 (Optimal Setting is a Gain of 1) | + | |
| - | * MU Desired Phase: Desired Phase Value for Phase to Voltage Converter to Optimize Mu Controller. The | + | |
| - | optimal setting is negative 6 (max of 16) . Register 0x27 bits 0-4 | + | |
| - | * Slope: Slope the mu contoller will lock onto Register 0x26 bit 6 (Optimal setting is Negative slope set bit to 0) | + | |
| - | * MU_DEL_Manual: | + | |
| - | search. It is best to set it to the middle of the delay line . The maximum Mu delay is 432, so set these bits to | + | |
| - | approximately 220. | + | |
| - | + | ||
| - | Sets the Mode in which the Controller searches: | + | |
| - | ^Mode^ Register: 0x26 Bits 4, 5^ | + | |
| - | |Search and Track (Optimal Setting)| 0x00| | + | |
| - | |Track Only| 0x01| | + | |
| - | |Search Only| 0x10| | + | |
| - | |Invalid| 0x11| | + | |
| - | + | ||
| - | Sets the Mode in which the search for the optimal phase is performed: | + | |
| - | ^Search Mode^ Register: 0x27 – Bits 5, 6^ | + | |
| - | |Down| 0x00| | + | |
| - | |Up| 0x01| | + | |
| - | |Up/Down (Optimal Setting)| 0x10| | + | |
| - | |Invalid| 0x11| | + | |
| - | Search GB: sets a GB from the beginning and end of the Mu Delay line in which the Mu controller will not enter | + | |
| - | into unless it does not find a valid phase outside the GB. Register 0x29 bits 0-4. Optimal value is Decimal 11. | + | |
| - | + | ||
| - | Tolerance: Sets the Tolerance of the phase search. Register 0x29 bit 7 | + | |
| - | * 0 – Not Exact. Can find a phase within 2 phases of the desired phase | + | |
| - | * 1- Exact. Finds the exact phase you are targeting (Optimal Setting) | + | |
| - | + | ||
| - | ContRST: Controls whether the controller will reset or continue if it does not find the desired phase | + | |
| - | * 0 – Continue (Optimal Setting) | + | |
| - | * 1 – Reset | + | |
| - | + | ||
| - | Phase Detector Enable: Register 0x24 bit 5. Enables the Phase Detector (Set to 1 to enable the Phase Detector) | + | |
| - | + | ||
| - | Phase Detector Comparator Boost: Optimizes the bias to the Phase Detector (Set to 1 to enable) | + | |
| - | + | ||
| - | Bias: Register 0x24 Bits 0-3: Manual Control of the bias if the Boost control is not enabled | + | |
| - | + | ||
| - | Duty Cycle Fix: Register 0x25 Bit 7 Enables the duty cycle correction in the Mu Controller. Recommended to | + | |
| - | always enable (Set to 1 to enable) | + | |
| - | Direction: Register 0x25 Bit 6 Sets the direction that the duty cycle will be corrected | ||
| - | * 0 – Negative (Optimal Setting) | ||
| - | * 1 - Positive | ||
| - | Offset: Register Register 0x25 Bit 0-5 Sets the Duty Cycle Correction manually | + | =====Troubleshooting===== |
| + | This section lists items to check and practices to use when debugging any unexpected performance of a board. If unexpected results occur: | ||
| + | * Check if the Voltage supply test points of the evaluation board has the correct value. | ||
| + | * Check if all (3) blue LEDs on the AD-DAC-FMC-ADP board is lit up. Reconnect | ||
| + | * Check if the SDP-H1 | ||
| + | * Power cycle both the SDP-H1/ | ||
| + | * Check on the Spectrum Analyzer if the DAC clock inputs are properly driven. For 300MHz clock using SDP-H1, the spectrum analyzer should detect a weak signal at 300MHz. For 2GHz clock using ADS7-V2, the spectrum analyzer should detect a weak signal at 2GHz. If not detected, check properly the clock source and connections. | ||
| + | * Disconnect and reconnect the SDP-H1 /ADS7-V2 and AD9739 evaluation board. Reopen DPG Lite software. | ||
| - | The status read back bits for the mu controller are as follows: | ||
| - | * MU_LCK: Register 0x2A bit 0 (value of 1 means the controller is locked) | ||
| - | * LST_LCK: Register 0x2A bit 1 (Value of 1 means the control lost lock) | ||
| - | In order to read back the present MU Delay and phase value, it is necessary to set the Read bit high and then | ||
| - | low before the values can be read back: | ||
| - | * Read: Register 0x26 Bit 3 | ||
| - | * Mu Delay Readback: Register 0x28 bits 0-7 and 0x27 bits 6,7 | ||
| - | * (Total of 9 bits in the read back the maximum Mu delay value is d432 or x1B0) | ||
| - | * MUD_PH_Readback: | ||
| - | In order to use the Mu controller in manual mode the following bits are utilized: | ||
| - | * Mu Controller Enable: Register 0x26 Bit 0 (Set to 0 to disable the controller) | ||
| - | * MU_DEL_Manual: | ||
| - | ==== LVDS Receiver Controls ==== | ||
| - | * RCV_LOOP - On (Register 0x10 bit 1 set to 1) | ||
| - | * RCV_ENA - On (Register 0x10 bit 0 set to 1) | ||
| - | * LCKTHR - 2 (Register 0x15 bits 0-4) | ||
| - | * RVCR_GAIN - 1 (Register 0x11 bit 0 set to 1) | ||
| - | * FINE_DELAY_MID - 7 (Register 0x11 bits 2-5) | ||
| - | * FINE_DELAY_SKEW - 2 (Register 0x13 bits 0-4) | ||
| - | * Sample_Delay: | ||
| - | Register 0x12 Optimal value is 166 which is the center of the delay line. The maximum delay value is d333 or x14D. | ||
| - | * DCI_Delay: Must be equal to the Sample_delay. Register 0x13 bits 4-7 Register 0x14 bits 0-5. Optimal value is also 166 which is the center of the delay line. The maximum delay value is d333 or x14D. | ||
| - | To ensure that the LVDS Controller is locked and tracking check the status of the following bits: | ||
| - | * RCVR Lock (Register 0x21 bit 0) This should be high if the controller is locked | ||
| - | * TRK_ON (Register 0x21 bit 3) This should be high if the controller is tracking | ||
resources/eval/dpg/ad9739-ebz.txt · Last modified: 15 Feb 2022 02:28 by Melissa Lorenz Lacanlale