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resources:eval:dpg:ad9739-ebz [26 Jun 2012 00:12] – headlines Michael Fowler | resources:eval:dpg:ad9739-ebz [21 Sep 2021 10:16] – [Quick Start Guide] Melissa Lorenz Lacanlale | ||
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- | ====== AD9739 | + | ======EVALUATING THE AD9739 |
- | ===== Getting Started with the AD9122 Evaluation Board ===== | + | |
- | ==== What's in the Box ==== | + | |
- | * AD9739-EBZ | + | =====Preface===== |
- | * Mini-USB Cable | + | This user guide describes both the hardware and software setup needed to acquire data capture from [[adi> |
- | | + | |
- | ==== Recommended Equipment | + | This guide shows how AD9739-R2-EBZ works with SDP-H1 or ADS7-V2 controller board developed by Analog Devices. Link to the previous user guide document is provided for customers who still have the DPG3 controller board. |
- | * Digital Pattern Generator (DPG2): ADI HSC-DAC-DPG-BZ | + | |
- | * +5Vdc Power Supply Ex: Agilent E3630A | + | =====Typical Setup===== |
- | * DAC Clock Source Ex: Rohde Schwarz SML 02 | + | {{ :resources: |
- | * Spectrum Analyzer Ex: Agilent PSAA or Rohde Schwarz FSU | + | <WRAP centeralign>// |
- | * PC: Windows PC with 2 or more USB ports | + | |
- | ==== Introduction | + | {{ :resources: |
- | The AD9739 Evaluation Board connects to the Analog Devices Digital Pattern Generator (DPG2) to allow for quick evaluation of the AD9739. The DPG2 allows the user to create many types of digital vectors | + | <WRAP centeralign>// |
- | ==== Software Installation ==== | + | |
- | The DAC Software Suite plus AD9739 Update should be installed on the PC prior connecting the hardware to the PC. The DAC Software Suite is included on the Evaluation Board CD, or can be downloaded from the DPG web site at http://www.analog.com/dpg. This will install DPGDownloader (for loading vectors into the DPG2) and the AD9739 SPI Controller application. | + | <note tip>Tip: Click on any picture in this guide to open an enlarged version.</ |
- | ==== Hardware Setup ==== | + | |
- | To operate the board, a power supply capable | + | |
- | ==== Evaluation Board Editions ==== | + | =====Helpful Files:===== |
- | The AD9739 Evaluation Board has four versions: “Normal” (AD9739-EBZ), “Mix Mode” (AD9739-MIX-EBZ), and “CMTS” (AD9739-CMTS-EBZ) and the newer AD9739-R2-EBZ. | + | * Download |
- | <note important> | + | * Data Sheet: |
- | The four editions differ only in the output stage configuration. The software used to evaluate all four boards is identical.</note> | + | * IBIS Model: [[adi> |
- | === R2 === | + | * Schematic: {{ : |
- | The new R2 board is designed to allow evaluation of the AD9739 | + | * Bill of Materials: {{ : |
- | === Normal | + | |
- | In normal mode, there is no filter and the only components are the 90Ω resistors to terminate the DAC outputs and the two transformers | + | |
- | (balun and center tap) as shown in Figure 3. (All customers should now use the AD9739-R2-EBZ board) | + | * PCB Gerber files: {{ : |
- | === Mix-Mode | + | |
- | The Mix-Mode configuration is targeted at applications using the 2nd and 3rd Nyquist zones using the analog mix mode. In this application, | + | * PCB BRD file: [[ftp:// |
- | === CMTS === | + | |
- | This configuration was for applications targeting cable infrastructure applications up to 1GSPS. The output configuration for this application is shown in Figure 4. In this configuration, | + | * PCB Layout PDF: {{ : |
- | ===== Getting Started | + | |
- | This quick-start will setup a single-tone output from the AD9739 to provide a brief introduction | + | =====Software Needed:===== |
- | ==== Enable Mu Controller ==== | + | * [[: |
- | In order to optimize | + | * [[: |
- | ==== Load Pattern from the DPG2 ==== | + | |
- | Open DPGDownloader (Start > Programs > Analog Devices > DPG > DPGDownloader). Ensure that “AD9739” is selected in the Evaluation Board drop-down list. For this evaluation | + | =====Hardware Needed:===== |
- | Click on Add Generated Waveform, and then Single Tone, as shown in Figure 6. A Single Tone panel will be added to the vector list. Start by entering | + | * [[adi> |
- | Next, in the lower portion of the screen, select “1: Single Tone” as the Data Vector. The other options can be left at their default.After the DPG2 is correctly setup, click the Download button ( ) in the lower right, then the Play button ( ) to begin vector playback into the AD9739. | + | * [[: |
- | ==== Enable LVDS Controller ==== | + | * Evaluation Kit |
- | Once the pattern is loaded into the DPG2 and running, the final step is to enable the LVDS Controller. In the AD9739 | + | * [[adi>AD-DAC-FMC]]-ADP High-Speed DAC Evaluation Board to FMC Adaptor Board |
- | Another way to verify that the controller is in the correct spot (and not on the edge) is to check the status of the four status bits which sample the rising edge of the DCI at four different phases. DCI PHS1should always be | + | * 5Vdc 2A Power Supply |
- | high, and DCI PHS3should always be low. The other bits will toggle | + | * PC with ACE and DPG Lite Software Applications |
- | correct timing. The ideal case is shown in Figure | + | * High-Frequency Continuous Wave Generator |
- | wider search around the DCI edge, and should reduce the toggling on PHS0and PHS2. This is usually required | + | * Signal/ |
- | when the DCI signal has a lot of jitter. | + | * USB-A to USB-Mini Cable |
- | ==== Result ==== | + | * (2) SMA Cables |
- | The final result of this setup should | + | * Power Supply |
- | ===== SPI Controller ===== | + | * The following are included |
- | The SPI controller software is broken | + | * 12Vdc 2.5A Wall Wart |
- | ==== SPI Settings and Powerdown/Reset ==== | + | * USB-A to USB-Mini Cable |
- | These bits (shown in Figure | + | * The following are included in ADS7-V2 Evaluation Kit: |
- | reset and individual power-down bits. Changing the SDIO DIR or DATADIR bits will cause the SPI controller application to stop functioning correctly. Do not change these bits. The Reset button is “sticky”, | + | * 12V 60W AC/DC Power Supply |
- | ==== Controller Clock Controls | + | * Power Cord |
- | The Controller Clock controls enable the Mu Controller and LVDS controllers. For normal operation, | + | * USB-A to USB-B Cable |
- | both of these should be enabled. The Clock GEN PDswitch powers down the clocking structure, and | + | |
- | should be left disabled for normal use. | + | =====Quick Start Guide===== |
- | The DAC current ouput has an adjustable full-scale value. The FSC Setoption allows for this adjustment. | + | - Attach |
- | After running | + | * If using **SDP-H1**, set clock input to **300 MHz and 0 dBm**. Connect SDP-H1 |
- | Mu Controller Clock Enable: Register 0x02 Bit 0 | + | * If using **ADS7-V2**, |
- | LVDS Controller Clock Enable: Register 0x02 Bit 1 | + | |
- | Analog Full-Scale Setting (10 bit Gain DAC 10-30mA adjustment): | + | * If using **SDP-H1**, The MU Controller Locked indicator |
- | 0x07 bits 0,1 | + | * If using **ADS7-V2**, The first three indicators should light up as shown in figure 2b. <WRAP centeralign> |
- | ==== Decoder Controller | + | - Double click the AD9739 Box to open chip view. |
- | Decoder Mode: Register 0x08 Bits 0,1 | + | * If using **SDP-H1**, |
- | 0x0 – Normal Mode | + | * If using **ADS7-V2**, |
- | 0x1 – Return | + | - Start DPG Lite or DPG Downloader. |
- | 0x2 – Mix Mode | + | * At the SDP-H1 |
- | ==== Cross Control ==== | + | * At the ADS7-V2 part of the software, the device part number |
- | CLKP Offset Setting: Register 0x24 Bits 0-3 | + | - In DPG Lite or DPG Downloader, from the **Add Generator Waveforms** pulldown menu, select **Single Tone** and apply the settings as shown in Figures 4a and 4b. |
- | CLKP Direction Bit: Register 0x24 Bit 4 | + | * When using SDP-H1, set **Data Rate** to 300 MHz and **Desired Frequency** |
- | CLKP Offset Setting: Register 0x25 Bits 0-3 | + | * When using ADS-V2, set **Data Rate** |
- | CLKP Direction Bit: Register 0x25 Bit 4 | + | - Continuing on setting |
- | Damp: Register 0x25 Bits 7 | + | - Select |
- | Mu Controller Enable: Register 0x26 Bit 0 (Set to 1 to enable the controller) | + | - Press the download arrow and then the play button. |
- | Mu Controller Gain: Register 0x26 Bits 1,2 (Optimal Setting is a Gain of 1) | + | |
- | MU Desired | + | |
- | optimal setting is negative 6 (max of 16) . Register 0x27 bits 0-4 | + | =====Troubleshooting===== |
- | Slope: Slope the mu contoller will lock onto Register 0x26 bit 6 (Optimal | + | This section lists items to check and practices |
- | MU_DEL_Manual: | + | * Check if the Voltage supply test points of the evaluation board has the correct value. |
- | search. It is best to set it to the middle of the delay line . The maximum Mu delay is 432, so set these bits to | + | * Check if all (3) blue LEDs on the AD-DAC-FMC-ADP board is lit up. Reconnect |
- | approximately 220. | + | * Check if the SDP-H1 |
- | Mode: Register: 0x26 Bits 4, 5 Sets the Mode in which the Controller searches: | + | * Power cycle both the SDP-H1/ADS7-V2 and the AD9739 evaluation board. |
- | 0x00 – Search and Track (Optimal Setting) | + | * Check on the Spectrum Analyzer if the DAC clock inputs are properly driven. For 300MHz clock using SDP-H1, the spectrum analyzer should detect a weak signal at 300MHz. For 2GHz clock using ADS7-V2, |
- | 0x01 – Track Only | + | * Disconnect and reconnect |
- | 0x10 – Search Only | + | |
- | 0x11 – Invalid | + | |
- | Search Mode: 0x27 – Bits 5, 6 Sets the Mode in which the search for the optimal phase is performed | + | |
- | 0x00 – Down | + | |
- | 0x01 – Up | + | |
- | 0x10 – Up/Down (Optimal Setting) | + | |
- | 0x11 – Invalid | + | |
- | Search GB: sets a GB from the beginning and end of the Mu Delay line in which the Mu controller will not enter | + | |
- | into unless it does not find a valid phase outside the GB. Register 0x29 bits 0-4. Optimal value is Decimal 11. | + | |
- | Tolerance: Sets the Tolerance of the phase search. Register 0x29 bit 7 | + | |
- | 0 – Not Exact. Can find a phase within 2 phases of the desired phase | + | |
- | 1- Exact. Finds the exact phase you are targeting (Optimal Setting) | + | |
- | ContRST: Controls whether the controller will reset or continue if it does not find the desired phase | + | |
- | 0 – Continue (Optimal Setting) | + | |
- | 1 – Reset | + | |
- | Phase Detector Enable: Register 0x24 bit 5. Enables the Phase Detector (Set to 1 to enable the Phase Detector) | + | |
- | Phase Detector Comparator Boost: Optimizes the bias to the Phase Detector (Set to 1 to enable) | + | |
- | Bias: Register 0x24 Bits 0-3: Manual Control of the bias if the Boost control is not enabled | + | |
- | Duty Cycle Fix: Register 0x25 Bit 7 Enables the duty cycle correction in the Mu Controller. Recommended to | + | |
- | always enable (Set to 1 to enable) | + | |
- | Direction: Register 0x25 Bit 6 Sets the direction that the duty cycle will be corrected | + | |
- | 0 – Negative (Optimal Setting) | + | |
- | 1 - Positive | + | |
- | Offset: Register Register 0x25 Bit 0-5 Sets the Duty Cycle Correction manually if Fix is not enabled | + | |
- | The status read back bits for the mu controller are as follows: | + | |
- | MU_LCK: Register 0x2A bit 0 (value of 1 means the controller is locked) | + | |
- | LST_LCK: Register 0x2A bit 1 (Value of 1 means the control lost lock) | + | |
- | In order to read back the present MU Delay and phase value, it is necessary to set the Read bit high and then | + | |
- | low before the values can be read back: | + | |
- | Read: Register 0x26 Bit 3 | + | |
- | Mu Delay Readback: Register 0x28 bits 0-7 and 0x27 bits 6,7 | + | |
- | (Total of 9 bits in the read back the maximum Mu delay value is d432 or x1B0) | + | |
- | MUD_PH_Readback: | + | |
- | In order to use the Mu controller in manual mode the following bits are utilized: | + | |
- | Mu Controller Enable: Register 0x26 Bit 0 (Set to 0 to disable the controller) | + | |
- | MU_DEL_Manual: Register 0x28 bits 0-7 and 0x27 bits 7,8. (Total of 9 bits | + | |
- | the maximum Mu delay value is d432 or x1B0) | + | |
- | ==== LVDS Receiver Controls | + | |
- | RCV_LOOP - On (Register 0x10 bit 1 set to 1) | + | |
- | RCV_ENA - On (Register 0x10 bit 0 set to 1) | + | |
- | LCKTHR - 2 (Register 0x15 bits 0-4) | + | |
- | RVCR_GAIN - 1 (Register 0x11 bit 0 set to 1) | + | |
- | FINE_DELAY_MID | + | |
- | FINE_DELAY_SKEW | + | |
- | Sample_Delay: | + | |
- | Register 0x12 Optimal value is 166 which is the center | + | |
- | value is d333 or x14D. | + | |
- | DCI_Delay: Must be equal to the Sample_delay. Register 0x13 bits 4-7 Register 0x14 bits 0-5. | + | |
- | Optimal value is also 166 which is the center of the delay line. The maximum delay value is | + | |
- | d333 or x14D. | + | |
- | o ensure that the LVDS Controller is locked and tracking | + | |
- | RCVR Lock (Register 0x21 bit 0) This should be high if the controller is | + | |
- | locked | + | |
- | TRK_ON (Register 0x21 bit 3) This should be high if the controller is tracking | + |