Differences

This shows you the differences between two versions of the page.

--- resources:eval:dpg:ad917x-fmc-ebz [23 Oct 2019 23:13] – [KCU-105 Setup] Arik Landsman
+++ resources:eval:dpg:ad917x-fmc-ebz [09 Feb 2022 21:19] (current) – [ADS7/ADS8-V1 Setup] Arik Landsman
@@ Line 4: / Line 4: @@
   * Mini USB cable
-**Note: if using the KCU-105 evaluation kit as a pattern generator, an additional board is needed. Be sure to order the AD-HSDACFX3-EBZ evaluation kit as well. Customers will need to order their own KCU-105 evaluation kit from Xilinx: http://www.xilinx.com/products/boards-and-kits/kcu105.html**
+=== Additional Components Needed for an ADS7 / ADS8-V1 Evaluation Platform ===
+  * Pattern generator board: ADS7 (up to 13Gbps SERDES) or ADS8-V1 (covers the full AD917x range): [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADS8-V1EBZ.html]]
-==== What's In The Box: AD-HSDACFX3-EBZ (Needed for use with the KCU-105 Only) ====
+**Note: if using the Xilinx KCU105 evaluation kit as a pattern generator, customers will need to purchase the following additional components:**
-  * FX3 Cypress Board + FMC Interconnect Board (pre-programmed and assembled for immediate use)
-  * Micro SD card containing FPGA image to be used with the KCU-105
-==== General Description ====
+=== Additional Components Needed for a KCU105 Evaluation Platform ===
+  * Xilinx KCU105 Evaluation Kit: http://www.xilinx.com/products/boards-and-kits/kcu105.html
+  * Cypress FX3 SuperSpeed Explorer Kit (CYUSB3KIT-003): https://www.cypress.com/documentation/development-kitsboards/cyusb3kit-003-ez-usb-fx3-superspeed-explorer-kit
+  * Cypress FX3 FMC Interconnect Board (CYUSB3ACC-005): https://www.cypress.com/documentation/development-kitsboards/cyusb3acc-005-fmc-interconnect-board-ez-usb-fx3-superspeed
+  * Micro SD Card
-The AD917x Evaluation Board Setup Guide provides details about how to set up the hardware and software for the evaluation kit.  This guide explains how to setup the KCU-105 and the ADS8 and AD917x-FMC-EBZ.  This evaluation kit will also support the Analog Devices ADS7 platform for lane rate configurations that are ≤12.5Gbps.  The DPGDownloader software will be used to set up the data vectors and FPGA SERDES mode configuration for the KCU-105 platform, ADS8 or ADS7 and the ACE software (Analysis | Control | Evaluation) will be used to set up the AD917x evaluation board, including the HMC7044 clock distribution chip on the board.
+===== General Description =====
+The AD917x Evaluation Board Setup Guide provides details about how to set up the hardware and software for the evaluation kit.  This guide explains how to setup the KCU105 and the ADS8 and AD917x-FMC-EBZ.  This evaluation kit will also support the Analog Devices ADS7 platform for lane rate configurations that are ≤12.5Gbps.  The DPGDownloader software will be used to set up the data vectors and FPGA SERDES mode configuration for the KCU105 platform, ADS8 or ADS7 and the ACE software (Analysis | Control | Evaluation) will be used to set up the AD917x evaluation board, including the HMC7044 clock distribution chip on the board.
 The AD917x-FMC-EBZ evaluation board can be driven by an external direct clock with DAC PLL off or the on-board clock from HMC7044 with DAC PLL on. The reference clock of HMC7044 can be provided by the on-board 122.88MHz crystal or the external signal generator.
@@ Line 25: / Line 31: @@
 ===== Hardware Setup =====
-==== ADS7/ADS8 Setup ====
+==== Clocking the AD917x-FMC-EBZ ====
+From the factory, the AD917X-FMC-EBZ is configured to generate all necessary clocks using an on-board clocking IC, the HMC7044. Using PLL2, The HMC7044 generates the lanerate/40 clock, two phase-aligned SYSREF clocks, and a reference for the AD917x's on-chip PLL to generate a DAC sampling clock (DACCLK). The reference for PLL2 is an on-board, 122.88MHz VCXO. Using PLL1, the 122.88MHz VCXO can be locked to an external reference via an SMA port at J41.
+=== Directly Clocking the AD917x-FMC-EBZ ===
+For some configurations, the user may be interested to use a custom clock source and provide the DACCLK directly to the CLK± pins of the AD917x (whether or not using the DACCLK PLL). In this case, remove C36 and C38 and populated C34 and C35 instead, as shown in the Figure 4. Connect a high-performance clock with >=12dBm output level to J34.
+** Clocking for a JESD204B link **
+When using a JESD204B link to the AD917x, the JESD204B link clocks are generated by the HMC7044's PLL2. The HMC7044 should be frequency-locked to common reference with the DAC sampling clock, via HMC7044's PLL1. PLL1 can lock the onboard 122.88MHz VCXO to external reference, or to an onboard XTAL (also 122.88MHz). The reference must be an integer-multiple of 122.88MHz , such as 3.84MHz , 7.68MHz, 15.36MHz, 30.72MHz, 61.44MHz, 122.88MHz, 245.76MHz or 491.52MHz.
+It is best to use a second, low phase noise, reference clock source with 0 dBm output level, connected to the SMA port at J41; the reference clock source must be frequency locked to a common reference with the DAC clock source. Two options exist: Two separate sources can be synchronized through the 10MHz INPUT/OUTPUT port in the back panel of the equipment; or alternatively, a unit such as the Rohde and Schwarz SMA100 has a convenient option for a secondary clock source, to generate the two external clocks from a single unit.
+** Clocking for NCO-only mode**
+When using the AD917x in NCO-only mode, without a JESD204B link, the only external clock needed is at J34. The HMC7044 is not used in this case.
+{{ :resources:eval:dpg:figure4_ad9172fmc.png?direct |}}
+Figure 4. Direct Clocking Option for DAC Clk± Pins
+==== ADS7/ADS8-V1 Setup ====
+<note important>NOTE: The ADS8-V1 covers the full range of the SERDES (JESD204B) lane rate of the device, up-to 16Gbps. The ADS7 is limited to a 13Gbps Lane rate, and may be a good economical alternative for users interested to operate at lower datarates.</note>
 The Cypress FX3 and interconnect board are not needed if the ADS7 or ADS8 board is used for data pattern generation. The hardware setup configuration when using the ADS7/ADS8 is as follows:
   - Connect the AD917x-FMC-EBZ board to the FMC connector on the ADS7 or ADS8.
@@ Line 34: / Line 65: @@
 {{ :resources:eval:dpg:ad9172:figure3_ads8_ad9172fmc.png?direct |}}
-Figure 3. Evaluation Board Kit Components Hardware Connection Setup with ADS8
+Figure 3. Evaluation Board Kit Components Hardware Connection Setup with ADS8-V1
-==== KCU-105 Setup ====
+==== KCU105 Setup ====
-The following items should be included in the evaluation kit (KCU-105 platform not included, purchased separately by the customer):
+In order to operate the AD917x evaluation board with the Xilinx KCU105, the customer must acquire the following items:
-   * Interconnect Board (connects FX3 board to the KCU-105 FMC connector) with Cypress FX3 board (only needed if using the KCU-105)
+  * AD917x-FMC-EBZ Evaluation Board
-   * USB2.0 Cable (connects FX3 board to USB port on a computer)
+  * Xilinx KCU105 Evaluation Kit: http://www.xilinx.com/products/boards-and-kits/kcu105.html
-   * AD917x-FMC-EBZ Evaluation Board
+  * Cypress FX3 SuperSpeed Explorer Kit (CYUSB3KIT-003): https://www.cypress.com/documentation/development-kitsboards/cyusb3kit-003-ez-usb-fx3-superspeed-explorer-kit
-   * Mini USB to USB Cable (connects mini USB port on evaluation board to USB port on a computer)
+  * Cypress FX3 FMC Interconnect Board (CYUSB3ACC-005): https://www.cypress.com/documentation/development-kitsboards/cyusb3acc-005-fmc-interconnect-board-ez-usb-fx3-superspeed
-   * MicroSD card with preprogrammed FPGA image to be used with DPGDownloader software (not needed for ADS7 or ADS8)
+  * Micro SD Card
-Connect the boards and cables to the KCU-105 board as shown in Figure 1 below.
+  * USB3.0 to USB Cable (connects FX3 board USB3.0 port to USB port on a computer)
+  * Mini USB to USB Cable (connects mini USB port on evaluation board to USB port on a computer)
+**Before connecting the hardware, the Cypress FX3 board and Micro SD Card must be programmed appropriately.**
+=== Programming the Cypress FX3 Board for KCU105 Setup ===
+**FX3 SDP Drivers:** {{ :resources:eval:dpg:ad9172:fx3_sdpdrivers_kcu105.zip |}}
+Begin by installing the FX3 SDP Drivers using the above link. When installing the drivers, ensure that the FX3 board is NOT plugged into your computer. A successful install will give an exit code of 256 in the printout while an unsuccessful install will try to restart your computer. If you experience an unsuccessful install, try re-running the driver installation executable. Some machines need to run this installer 3 times before the drivers are installed. You may receive a notification that newer drivers have already been installed—in this case, the installer will automatically abort installation as expected.
+You can confirm proper installation by following these steps:
+  - Using the USB3.0 cable, plug the FX3 FMC module into your computer WITHOUT the KCU105 connected.
+  - Open Device Manager.
+  - Confirm successful driver installation by verifying the presence of “High Speed Converter USB3.0 Evaluation Platform” under “ADI Development Tools” as shown below:{{ :resources:eval:dpg:ad9172:figure16_fx3_device_manager.png?400 |}}
+If you have confirmed successful driver installation, you can proceed to the next section which covers the FPGA image. If you do not see the device “High Speed Converter USB3.0 Evaluation Platform”, look for a device named “FX3” with a warning message. If you cannot locate the device “High Speed Converter USB3.0 Evaluation Platform” or the device “FX3”, try reinstalling the FX3 SDP Drivers.
+Most FX3 boards come preprogrammed with ADI’s firmware, but there are some instances when this firmware is missing. If you have installed the FX3 SDP Drivers but only see an “FX3” device with a warning listed under Device Manager, then your FX3 board is not preprogrammed. In this case, follow these steps to program your FX3 board:
+**FX3 Firmware Image:** {{ :resources:eval:dpg:ad9172:fx3firmware_r2_06032016.zip |}}
+  - Download and install the Cypress SDK via http://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-software-development-kit.
+  - Open the "USB Control Center" tool located at: All Programs >> Cypress >> EZ-USB FX3 SDK >> Cypress USBSuite >> Control Center
+  - **Connect jumper J4** on the FX3 and connect the FX3’s USB cable to your computer. The FX3 will appear as "Cypress USB Bootloader".{{ :resources:eval:dpg:ad9172:figure17_fx3_programming_step_3.png?400 |}}
+  - Click on the "Cypress USB Bootloader" and select the I2C EEPROM option from the Program menu. Note: if you are not presented with a file selection dialog after clicking I2C EEPROM, then your FX3 needs additional programming. On the FX3 board, press the “reset” switch next to the USB3.0 connector and repeat Step #4.{{ :resources:eval:dpg:ad9172:figure18_fx3_programming_step_4.png?400 |}}
+  - Select the FX3 firmware image (image can be downloaded at the start of this section) when prompted by the file selection dialog.
+  - After the programming finishes, **disconnect jumper J4** and reset the FX3 via the pushbutton switch near the USB3.0 connector.
+  - If successful, the "Cypress USB Bootloader" entry is removed from the list of devices in the USB Control Center.
+As described earlier, successful firmware installation can be confirmed by following these steps:
+  - Using the USB3.0 cable, plug the FX3 FMC module into your computer WITHOUT the KCU105 connected.
+  - Open Device Manager.
+  - Confirm successful firmware installation by verifying the presence of “High Speed Converter USB3.0 Evaluation Platform” under “ADI Development Tools” as shown below:{{ :resources:eval:dpg:ad9172:figure16_fx3_device_manager.png?400 |}}
+=== Programming the Micro SD Card for KCU105 Setup ===
+**FPGA Image:** {{ :resources:eval:dpg:ad9172:kcu105_micro_sd_files.zip |}}
+Download the KCU105 FPGA image files and copy them to the MicroSD card so that the xilinx.sys file and kcu105 folder are at the top level of the MicroSD card:
+{{ :resources:eval:dpg:ad9172:figure19_fx3_micro_sd_fpga_files.png?400 |}}
+=== KCU105 Hardware Setup ===
+Connect the boards and cables to the KCU105 board as shown in Figure 1 below.
 {{ :resources:eval:dpg:ad9172:figure1_kcu_ad9172fmc.png?direct |}}
 Figure 1. Evaluation Board Kit Components Hardware Connection Setup
-Connect a reference clock frequency to the “Board Ref Clock” connection shown in Figure 1 (SMA connector J4).  This is the configuration required any time the evaluation board is to be measured and used. Turn on the KCU-105 power and plug in both USB cables to the host computer.
+Connect a reference clock frequency to the “Board Ref Clock” connection shown in Figure 1 (SMA connector J4).  This is the configuration required any time the evaluation board is to be measured and used. Turn on the KCU105 power and plug in both USB cables to the host computer.
-=== Using KCU-105 with DPG Downloader ===
+=== Using KCU105 with DPG Downloader ===
-The KCU-105 board requires some additional setup steps to be compatible with the DPGDownloader software.  A Micro-SD card that contains the FPGA image used with DPGDownloader is included in the evaluation kit.  Before powering on the KCU105 unit, this Micro-SD card should be inserted into the appropriate slot on the bottom right-hand side of the KCU105 evaluation board as shown in Figure 1.  In order to boot up the KCU105 board using the image from the Micro-SD card, ensure that the DIP switch settings on SW15 are set according to Figure 2 below.
+The KCU105 board requires some additional setup steps to be compatible with the DPGDownloader software, and these steps only need to be done **once** to properly configure the FPGA for future use with DPGDownloader. Before powering on the KCU105 unit, insert the Micro SD card with FPGA image into the appropriate slot on the bottom right-hand side of the KCU105 evaluation board as shown in Figure 1. Be certain to verify that the Micro SD card clicks into place when inserted. In order to boot up the KCU105 board using the image from the Micro SD card, ensure that the DIP switch settings on SW15 are set according to Figure 2 below.
 {{ :resources:eval:dpg:ad9172:figure2_kcuswitch.png?direct |}}
 Figure 2. KCU105 DIP Switch Settings for Loading Image from Micro-SD Card
-Once these steps are complete, the KCU105 board can be powered on and plugged into the USB ports on the host PC. This step only needs to be done once in order to set up the FPGA board properly for any future use with DPGDownloader software.
+Once these steps are complete, the KCU105 board can be powered on and plugged into the USB ports on the host PC. After powering on the KCU105, wait approximately 10 seconds so that the KCU105 has adequate time to load the FPGA image. If the KCU105's LEDs begin flashing immediately after power on, then the FPGA image has not been loaded correctly. In this case, remove the Micro SD card, confirm that the appropriate files are stored on the card, and repeat the above procedure. Be sure to verify that your Micro SD card is not being encoded when you write the FPGA image to it. Proper FPGA image programming can be confirmed by looking at the 3 LEDs near the KCU105's power switch--these 3 LEDs should be toggling in a heartbeat pattern.
-==== DC Test/NCO Mode Without ADS7/ADS8/KCU105 ====
+==== Other FPGA Development Kits====
+The AD917x-FMC-EBZ complies with the VITA57.1 standard. Thus, the AD917x-FMC-EBZ can be used with any FMC-compliant FPGA development kit. The AD917x has a convenient crossbar switch, which allows to remap the physical lanes routed to its SERDESx+/- pins on the PCB ("physical lanes") to the internal SERDES lanes within the JESD204B IP of the AD917x ("Logical lanes"). Any physical lane can be mapped to any of the logical lanes on-chip. For more details please refer to the Crossbar Switch section in the AD917x's datasheet.
+==== NCO-only Mode ("DC Test Mode") Without ADS7/ADS8/KCU105 ====
-The AD917x can work in DC TEST/NCO mode without ADS7/ADS8/KCU105 in non-(1x-1x) operating modes, but it has to run from an external power supply. In this case, DO NOT CONNECT the AD917x-FMC-EBZ board to the ADS7/ADS8/KCU105. Instead, connect +12V to TP41 (red), GND to TP42 (black). The external power supply should have capacity for 1A of current. Put the jumper on JP71 for powering on the PIC and USB port. If using an external clock source, connect a low phase noise, high frequency clock source to J34. In addition, connect the spectrum analyzer to the SMA connector, J1 or J2.
+The AD917x can work in NCO-only mode, without ADS7/ADS8/KCU105. In this case, **DO NOT CONNECT** the AD917x-FMC-EBZ board to the ADS7/ADS8/KCU105. Instead, connect an external +12V power supply to TP41 (red) and GND to TP42 (black). The external power supply should have capacity for at least 1A of current. Install the jumper on JP71 for powering on the PIC and USB port.
+If using an external clock source, connect a low phase noise, high frequency clock source to J34. See the "Directly Clocking the AD917x-FMC-EBZ" section for more details.
-==== Direct Clock the AD917x ====
+The outputs of the AD917x can be captured at the SMA connectors: J1 for DAC0; J2 for DAC1; and J3 for CLKOUT.
-For some configurations, the DAC on-chip PLL may not support the desired DAC sampling clock. In order to direct clock the CLK± pins of the AD917x, rotate C36 and C38 to instead be populated on C34 and C35 as shown in the Figure 4. Connect a high-performance clock with >=12dBm output level to J34 for the direct clock option. A second low phase noise, high frequency clock source (3.84MHz , 7.68MHz, 15.36MHz, 30.72MHz, 61.44MHz, 122.88MHz, 245.76MHz and 491.52MHz) with 0 dBm output level that is the reference clock of the HMC7044 should be connected to the SMA connector J41; the two clock sources should be synchronized through the 10MHz INPUT/OUTPUT port in the back panel. A unit such as the Rohde and Schwarz SMA100 has a convenient option for a secondary signal source, and using it will ensure the two clocks are synchronized.
+Some applications may be more sensitive to clock spurious. To prevent any spurious coupling from the onboard HMC7044 onto the AD917x output, the HMC7044 may be kept in reset:
-{{ :resources:eval:dpg:figure4_ad9172fmc.png?direct |}}
+  - reset the board in ACE (Reset Board button in the "AD917x-FMC-EBZ" view)
-Figure 4. Direct Clocking Option for DAC Clk± Pins
+  - in the Wizard, under Eval System Option select chip to configure: "AD917x Only". This will keep the HMC7044 in reset after step #1.
+  - Under DC Test Mode, select the option "Main" or "Channel" to enable the NCO-only mode
+  - Under SERDES Interface, set the link mode and interpolation (this will apply a clock to the corresponding datapaths. E.g. dual-link to enable both datapath0 and datapath1, that would feed DAC0 and DAC1 respectively)
+  - Under Clock frequencies, set the Input Data Rate to set the DAC Clock Rate. DAC Clock Rate = Data Rate * Interpolation.
-==== DC Test/NCO Mode Without ADS7/ADS8/KCU105 ====
-The AD917x can work in DC TEST/NCO mode without ADS7/ADS8/KCU105 in non-(1x-1x) operating modes, but it has to run from an external power supply. In this case, DO NOT CONNECT the AD917x-FMC-EBZ board to the ADS7/ADS8/KCU105. Instead, connect +12V to TP41 (red), GND to TP42 (black). The external power supply should have capacity for 1A of current. Put the jumper on JP71 for powering on the PIC and USB port. If using an external clock source, connect a low phase noise, high frequency clock source to J34. In addition, connect the spectrum analyzer to the SMA connector, J1 or J2.
 ===== Using DPGDownloader Software =====
 Launch the DPGDownloader software from the Start Menu (Start → All Programs → Analog Devices → DPG → DPG Downloader). When the program starts the DPG Panel should look recognize the evaluation board connected as shown in the AD917x panel being displayed as shown in Figure 5.  The desired SERDES JESD204B mode can be selected by using the “JSED Mode” drop-down menu.  If running in Dual Link mode, check the “Dual Link” checkbox on the panel to enable the second link options.  Use the “Add Generated Waveform” drop-down menu to create vectors to send to the evaluation board as desired.
-//Note: If using the KCU-105, first power up the KCU105 board and wait for the heartbeat LEDs shown in Figure 1 to begin flashing. Then open up DPGDownloader and ensure the Configuration Version displays 11/07/16, confirming that the FPGA image is loaded properly from the microSD card. If this does not display or if the KCU105 has been powered off and back on again, reselect the AD917x from the Evaluation Board dropdown menu to reinitialize the panel and the configuration version should display properly.
+//Note: If using the KCU105, first power up the KCU105 board and wait for the heartbeat LEDs shown in Figure 1 to begin flashing. Then open up DPGDownloader and ensure the Configuration Version displays 11/07/16, confirming that the FPGA image is loaded properly from the microSD card. If this does not display or if the KCU105 has been powered off and back on again, reselect the AD917x from the Evaluation Board dropdown menu to reinitialize the panel and the configuration version should display properly.
 //
@@ Line 171: / Line 247: @@
 The raw macro file will be saved using ACE syntax, which is not easily readable. To remedy this, the ACE software download includes the Macro to Hex Conversion Tool. The user can choose to include or exclude register write, reads, and/or comments in the conversion. The file pathways for the source and save paths should be the same, except that one should be an .acemacro file and the other should be a .txt file. The “Convert” button converts and opens the converted text file, which is easier to read. The conversion tool can also convert back to an .acemacro file if desired. The Macro to Hex converter tool is located in the start menu under "All Programs" --> "Analog Devices" --> "ACE" --> "Tools".
+<note important>NOTE: The latest version of ACE includes a new "Generate" option to output the register hex format directly and the Macro Converter is deprecated.</note>
 <WRAP column 40%>
 {{ :resources:eval:user-guides:ad9122_m2hconvert_5.png }}

Wiki

Analog Devices Wiki

Differences

Analog Devices Wiki

Differences

Page Tools