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| resources:eval:dpg:ad9154-m6720-ebz [26 Feb 2015 22:14] – 35 Larry Welch | resources:eval:dpg:ad9154-m6720-ebz [08 Jan 2021 11:03] (current) – Fixed bad link for AD9154-ADRF6720-EBZ Ioana Chelaru | ||
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| - | ====== AD9154-M6720-EBZ Evaluation Board Quick Start Guide ====== | + | ====== AD9154-ADRF6720-EBZ Evaluation Board Quick Start Guide ====== |
| - | ===== Getting Started with the AD9154-M6720-EBZ Evaluation Board and Software ===== | + | ===== Getting Started with the AD9154-ADRF6720-EBZ Evaluation Board and Software ===== |
| ==== What's in the Box ==== | ==== What's in the Box ==== | ||
| - | * [[adi> | + | * [[adi>AD9154|AD9154-ADRF6720-EBZ]] |
| * Evaluation Board CD | * Evaluation Board CD | ||
| * Mini-USB Cable | * Mini-USB Cable | ||
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| * Two Sinusoidal Clock Sources | * Two Sinusoidal Clock Sources | ||
| * Spectrum Analyzer | * Spectrum Analyzer | ||
| - | * Oscilloscope | ||
| * Data Pattern Generator Series 3 (DPG3) | * Data Pattern Generator Series 3 (DPG3) | ||
| ===== Introduction ====== | ===== Introduction ====== | ||
| - | The AD9154-M6720-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal processing RF Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9154-M6720-EBZ via its JESD204B lanes. The AD9154-M6720-EBZ includes an AD9154 and two ADRF6720-27 Wideband Quadrature Modulators with Integrated PLL and VCO. There is a board level passive low pass filter between the output of each AD9154 DAC and its corresponding ADRF6720-27 baseband input. The Evaluation Board (EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock used by the DPG3. | + | The AD9154-ADRF6720-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal processing RF Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9154-M6720-EBZ via its JESD204B lanes. The AD9154-M6720-EBZ includes an AD9154 and two ADRF6720-27 Wideband Quadrature Modulators with Integrated PLL and VCO. There is a board level passive low pass filter between the output of each AD9154 DAC and its corresponding ADRF6720-27 baseband input. The Evaluation Board (EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock used by the DPG3. |
| ===== AD9154 and ADRF6720-27 Evaluation Software ===== | ===== AD9154 and ADRF6720-27 Evaluation Software ===== | ||
| The AD9154 and ADRF6720-27 Evaluation software runs on the easy-to-use SPIPro graphical user interface (GUI). It is included on the Evaluation Board CD. | The AD9154 and ADRF6720-27 Evaluation software runs on the easy-to-use SPIPro graphical user interface (GUI). It is included on the Evaluation Board CD. | ||
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| b. Select JESD Mode 0. | b. Select JESD Mode 0. | ||
| - | c. Uncheck the “Subclass 1” box | + | c. Uncheck the “Subclass 1” box. |
| d. Select “2” for Interpolation. | d. Select “2” for Interpolation. | ||
| e. Press the “Configure DAC and Clock” Button | e. Press the “Configure DAC and Clock” Button | ||
| - | f. The JESD204B PLL Lock Readback light should turn green and register bit settings will be populated. The GUI will look like Figure 4, except that values in “CodeGrpSync”, | + | |
| + | f. The JESD204B PLL Lock Readback light should turn green and register bit settings will be populated. The GUI will look like Figure 4, except that values in “CodeGrpSync”, | ||
| g. Load Register Settings into the ADRF6720 devices by clicking “Restore Registers from File” and locating “ADRF6720.csv”. This should be located at the install directory for the AD9154 SPIPro application. | g. Load Register Settings into the ADRF6720 devices by clicking “Restore Registers from File” and locating “ADRF6720.csv”. This should be located at the install directory for the AD9154 SPIPro application. | ||
| + | |||
| h. Click on “ADRF6720” tab for Mod 1 and confirm the GUI matches Figure 5 below. | h. Click on “ADRF6720” tab for Mod 1 and confirm the GUI matches Figure 5 below. | ||
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| </WRAP center> | </WRAP center> | ||
| i. Click on “ADRF67202” tab for Mod 2 and confirm the GUI matches Figure 6 below. | i. Click on “ADRF67202” tab for Mod 2 and confirm the GUI matches Figure 6 below. | ||
| - | {{: | + | {{: |
| | Figure 6. Configured SPIPro ADRF67202 tab of the AD9154 SPI software | | Figure 6. Configured SPIPro ADRF67202 tab of the AD9154 SPI software | ||
| 4. DPG Downloader Start Up Sequence | 4. DPG Downloader Start Up Sequence | ||
resources/eval/dpg/ad9154-m6720-ebz.1424985298.txt.gz · Last modified: 26 Feb 2015 22:14 by Larry Welch