This version is outdated by a newer approved version.
This version (04 Aug 2022 07:44) is a draft.
Approvals: 0/1The Previously approved version (10 Jul 2020 19:20) is available.
This version (04 Aug 2022 07:44) is a draft.Approvals: 0/1The Previously approved version (10 Jul 2020 19:20) is available.
This is an old revision of the document!
Table of Contents
EVALUATING THE AD9154 DIGITAL-TO-ANALOG CONVERTER
Preface
This user guide describes both the hardware and software setup needed to acquire data capture from AD9154-FMC-EBZ evaluation board to characterize AD9154 16-bit 2.4Gsps quad JESD204B signal processing RF Digital to Analog Converter.
The AD9154-FMC-EBZ is an FMC mezzanine card and connects to an ADS7-V2 or ADS8-V1 data pattern generator system. The ADS7-V2/ADS8-V1 automatically formats the data and sends it to the AD9154-FMC-EBZ via its JESD204B lanes. +12V, +3.3V, and VADJ power supply rails are provided by the ADS7-V2/ADS8-V1 system via the FMC connector P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK clock used by the ADS7-V2/ADS8-V1. There is also an FMC standard I2C bus that is used by the ADS7-V2/ADS8-V1 to identify the AD9154-FMC-EBZ. This I2C interface is implemented in software in the AD9154-FMC-EBZ PIC processor (XU1). All ADS7-V2/ADS8-V1 to/from AD9154-FMC-EBZ interface signals are connected via the FMC connector P1.
AD9154 Evaluation Software
The AD9154 Evaluation Board software runs on the ADI ACE graphical user interface (GUI). ACE is included on the Evaluation board CD. Registers on the AD9154 and AD9516 products are programmed by the ACE software via a USB cable connecting the user’s PC to the AD9154-FMC-EBZ XP2 connector. Software in the AD9154-FMC-EBZ PIC processor (XU1) provides the interface between the USB bus and the SPI busses of the AD9154 and AD9516.
Hardware Setup
Figure 1 shows the block diagram of the set-up.
| Figure 1. AD9154-FMC-EBZ Lab Block Diagram |
| Figure 2. Top and Bottom view of AD9154-FMC-EBZ |
A spectrum analyzer should be connected to the EVB SMA connector J4. Connect SMA connectors J5, J14 and J17 of the EVB to an oscilloscope. The evaluation board connects to the ADS7 through the connector P1. The PC should be connected to the EVB using the mini-USB connector XP2. Figure 1 shows a block diagram of the set-up.
Clock input:
A low phase noise high frequency clock source should be connected to the SMA connector J1. As seen in the schematic of AD9154-FMC-EBZ, the onboard clock input to J1 is split between the AD9154 and the onboard AD9516 clock fanout buffer, routed to its CLK pins (labeled “FIN” in ACE). A number of clocking options are available on the AD9154-FMC-EBZ:
- direct DACCLK signal to the AD9154. The DACCLK is also routed to the AD9516's CLK pins (“FIN”) to generate the bitrate/40 clock that is needed to establish a JESD204B link.
- a reference clock to the AD9154's DACCLK PLL. In this case, the reference must be high enough to allow AD9516 to divide down FIN to the correct bitrate/40 rate. The bitrate is the lanerate of the JESD204B SERDES.
The AD9516 generates the bitrate/40 needed to establish a JESD204B link. If a JESD204B link needs to be established, it is best to supply J1 with a frequency equal to the target DACCLK. This will guarantee that FIN is high enough to generate BR/40 at the correct rate. AD9516 can then generate the reference to the AD9154's DACCLK PLL.
If option #1 is needed, the J1 input is split between the AD9154 and the AD9516.
If option #2 is needed, AD9154 may receive a reference clock either from the AD9516, as a divided down version of FIN, or directly from the J1 pin. In either case, the J1 input must be high enough to guarantee that the AD9516 can generate a bitrate/40 clock.
Getting Started
The PC software is included in the CD shipped with the EVB. The installation will include the software as well as all the AD9154 EVB files including schematic, board layout, datasheet, this quick start guide and other files.
Initial Set-Up
1. Install the customer evaluation board software and support files, including DPGDownloader and ACE GUI on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings.
2. Plug the AD9154-FMC-EBZ into port FMC_1 of the ADS7 System. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB as shown in Figure 1.
3. Connect the ADS7 unit to your PC via USB and turn on the ADS7.
4. Connect SMA connector J5 to a spectrum analyzer, connect SMA connectors J17, J4 and J14 to an oscilloscope.
Single Tone Demonstration
Single Tone Demo Lab Bench Configuration Procedure:
These settings configure the AD9154 to output a 180Mhz 0dbFS sine wave using the ADS7 on all four AD9154 DACs.
- Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1500MHz, and the output level to 3dBm. The spectrum analyzer can be configured as shown in Figure 8 with a resolution bandwidth of 300kHz. Choose an Input Attenuation of 22dB.
| Figure 3. Initial DPG Downloader Panel |
Single Tone Demo Hardware and Software Start Up Procedure:
1. Run DPG Downloader from Start→Analog Devices→DPG→DPG Downloader. The DPG Downloader GUI will say Evaluation Board: AD9154 and Port Configuration: JESD204B as shown in Figure 3. At this point, the ADS7 FMC power supplies will be turned on. Powering the EVB.
2. Open ACE from Start→Analog Devices→ACE. ACE will come up and display the initial ACE page shown in figure 4a.
3. Press the AD9154 icon and populate the AD9154 initialization wizard as shown in figure 4b, JESD mode 0, Interpolation 2. Leave all other settings in their default state. Press rhe APPLY button. JESD204B PLL lock will turn green as shown in figure 4c. Press the AD9154 icon in the initialization wizard tab. The AD9154 block diagram view will appear populated as shown in figure 4d.
| Figure 4a. Initial ACE page for AD9154-FMC-EBZ |
| Figure 4b. ACE AD9154 Initialization Wizard tab with selections made |
| Figure 4c. ACE AD9154 Initialization Wizard tab after pressing APPLY |
| Figure 4d. ACE AD9154 Block Diagram View after Initialization |
4. In DPG Downloader Window Select Single Tone under the Add Generated Waveforms Tab. Set Data Rate: 750Mhz, Desired Frequency: 180Mhz, Amplitude: 0dbFS, Uncheck Unsigned Data, Check Generate Complex Data (I&Q)
5. Select JESD Mode: Mode 0, Select Subclass 0
6. Populate the data playback selections for each DAC output as shown in Figure 5.
7. Click Download button and click Play button. The signals shown in figures 6 and 7 will appear on the DAC outputs (J17, J4, J5, and J14), Serial Line Rate will be 7.5Gbps. The green SYNC check mark indicates that the JESD204B link is up and running.
| Figure 5. AD9154-FMC-EBZ Fully Configured DPG Downloader Display |
8. Here’s what you will see on DAC0, DAC1, and DAC3 on the scope
9. Here is what you will see at the output of DAC2 on the Spectrum Analyzer.
| Figure 6. DAC Output Spectrum Analyzer Display |
| Figure 7. DAC Outputs Scope Display |
resources/eval/dpg/ad9154-ace-fmc-ebz.1659591855.txt.gz · Last modified: 04 Aug 2022 07:44 by Shine Cabatan