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resources:eval:dpg:ad9142a-m5372-ebz [07 Aug 2013 11:33] – [Single-Tone Test] Patrick Xuan | resources:eval:dpg:ad9142a-m5372-ebz [15 Jun 2017 19:49] – Bailey Meyer | ||
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* 2 Sinusoidal Clock Sources | * 2 Sinusoidal Clock Sources | ||
* Spectrum Analyzer | * Spectrum Analyzer | ||
- | * Data Pattern Generator Series 2 (DPG2) | + | * Data Pattern Generator Series 2 or 3 (DPG) |
- | == Introduction | + | ==== Introduction |
- | The AD9142A-M5372-EBZ connects to a DPG2 for quick evaluation of the AD9142A, a high-speed, signal processing Digital to Analog Converter. The DPG2 automatically formats the data and sends it to the AD9142A-M5372-EBZ, | + | The AD9142A-M5372-EBZ connects to a DPG for quick evaluation of the AD9142A, a high-speed, signal processing Digital to Analog Converter. The DPG automatically formats the data and sends it to the AD9142A-M5372-EBZ, |
===== AD9142A Evaluation Software ===== | ===== AD9142A Evaluation Software ===== | ||
- | The AD9142A Evaluation Board software has an easy-to-use graphical user interface (GUI). It is included on the Evaluation Board CD, or can be downloaded from the DPG website at http:// | + | The AD9142A Evaluation Board software has an easy-to-use |
===== Hardware Setup ===== | ===== Hardware Setup ===== | ||
- | Connect +5.0V to P5, GND to P6. One low phase noise high frequency clock source should be connected to the SMA connector, J1 (AD9516_CLKIN). The other low phase noise high frequency clock source should be connected to the SMA connector, J15 (LO_IN), and the spectrum analyzer should be connected to the SMA connector, J6. The evaluation board connects to the DPG2 through the connectors P1 and P2. The PC should be connected to the EVB using the mini-USB connector XP2 after installation of the Evaluation Board software. Figure 1 shows the block diagram of the set-up. | + | Connect +5.0V to P5, GND to P6. One low phase noise high frequency clock source should be connected to the SMA connector, J1 (AD9516_CLKIN). The other low phase noise high frequency clock source should be connected to the SMA connector, J15 (LO_IN), and the spectrum analyzer should be connected to the SMA connector, J6. The evaluation board connects to the DPG through the connectors P1 and P2. The PC should be connected to the EVB using the mini-USB connector XP2 after installation of the Evaluation Board software. Figure 1 shows the block diagram of the set-up. |
<WRAP center> | <WRAP center> | ||
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</ | </ | ||
===== Getting Started ===== | ===== Getting Started ===== | ||
- | The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http:// | + | The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http:// |
- | ==== Initial Set-Up ==== | + | ==== ACE ==== |
+ | === Initial Set-Up === | ||
+ | 1. Install the DPG Downloader and ACE software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. \\ \\ | ||
+ | 2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. \\ \\ | ||
+ | 3. Connect the DPG unit to your PC and turn on the unit. \\ \\ | ||
+ | === Single-Tone Test === | ||
+ | These settings configure the AD9142A to output a sine wave using the DPG and ACE and allow the user to view the single-tone performance at the IQMOD output, under the condition: Fdata = 350MHz, 4X interpolation, | ||
+ | 1. To begin, open ACE from the start window. It can be found by following the file path to the program or by searching in the Windows search bar for “ACE.” The {{: | ||
+ | |||
+ | If the board is connected properly, ACE will detect it and display it on the Start page under //Attached Hardware//. Double click this board. | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | Ensure that the {{: | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | 2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1400MHz, and the output level to 6dBm. The spectrum analyzer can be configured with Center Frequency = 2050 MHz, Span = 200 MHz, and Resolution Bandwidth of 30 kHz. Choose Input Attenuation to be 24dB. This can be adjusted later if indications are that the analyzer is causing degradations. \\ \\ | ||
+ | 3. Follow the sequence below to configure the AD9142A using ACE. \\ \\ | ||
+ | a. Click " | ||
+ | |||
+ | <WRAP column 40%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP column 55%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP column 40%> | ||
+ | <WRAP centeralign> | ||
+ | </ | ||
+ | <WRAP column 55%> | ||
+ | <WRAP centeralign> | ||
+ | </ | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | |||
+ | b. Double click on the AD9142A component on the board diagram. This brings up the chip diagram. Set all the settings to match those in the chip diagram below, and click "Apply Changes." | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | c. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9142A, as indicated in the " | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | d. Click on "Add Generated Waveform," | ||
+ | e. Click Download ({{: | ||
+ | 4. The current on the 5V supply should read about 1310mA. \\ | ||
+ | |||
+ | <WRAP center> | ||
+ | | {{ : | ||
+ | | Figure 9. AD9142A-M5372 Eval Board output Spectrum | ||
+ | </ | ||
+ | ==== SPI Software ==== | ||
+ | === Initial Set-Up | ||
1. Install the DPG Downloader and AD9142A SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. \\ \\ | 1. Install the DPG Downloader and AD9142A SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. \\ \\ | ||
2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. \\ \\ | 2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. \\ \\ | ||
- | 3. Connect the DGP2 unit to your PC and turn on the unit. \\ \\ | + | 3. Connect the DPG unit to your PC and turn on the unit. \\ \\ |
- | ==== Single-Tone Test ==== | + | === Single-Tone Test === |
- | These settings configure the AD9142A to output a sine wave using the DPG2 and allow the user to view the single-tone performance at the IQMOD output, under the condition: Fdata = 350MHz, 4X interpolation, | + | These settings configure the AD9142A to output a sine wave using the DPG and allow the user to view the single-tone performance at the IQMOD output, under the condition: Fdata = 350MHz, 4X interpolation, |
1. 1. To begin, open the AD9142A SPI application (Start > All Programs > Analog Devices > SPIPro). The screen should look similar to Figure 3. \\ \\ | 1. 1. To begin, open the AD9142A SPI application (Start > All Programs > Analog Devices > SPIPro). The screen should look similar to Figure 3. \\ \\ | ||
<WRAP center> | <WRAP center> | ||
| {{: | | {{: | ||
- | | Figure | + | | Figure |
</ | </ | ||
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d. There may be a few registers highlighted in red. The red highlights mean mismatches between the SPI read and write values in the software. Clicking “Read All Registers” reads back all the current values in the registers, which should resolve the highlights. \\ \\ | d. There may be a few registers highlighted in red. The red highlights mean mismatches between the SPI read and write values in the software. Clicking “Read All Registers” reads back all the current values in the registers, which should resolve the highlights. \\ \\ | ||
e. Toggle register “FIFO SPI RESET REQUEST”. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers. \\ \\ | e. Toggle register “FIFO SPI RESET REQUEST”. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers. \\ \\ | ||
- | f. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9142A, as indicated in the “Evaluation Board” drop-down list, and select it. For this evaluation board, LVDS is the only valid Port Configuration, | + | f. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9142A, as indicated in the “Evaluation Board” drop-down list, and select it. For this evaluation board, LVDS is the only valid Port Configuration, |
<WRAP center> | <WRAP center> | ||
| {{ : | | {{ : | ||
- | | Figure | + | | Figure |
</ | </ | ||
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| {{ : | | {{ : | ||
- | | Figure | + | | Figure |
</ | </ | ||
h. Click Download ({{: | h. Click Download ({{: | ||
- | i. Go back to the AD9142A SPI software and toggle the “FIFO SPI RESET REQUEST” button (from 0 to 1 and back to 0) to reset the FIFO. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers. The AD9142A SPI software and the spectrum analyzer should look like Figure | + | i. Go back to the AD9142A SPI software and toggle the “FIFO SPI RESET REQUEST” button (from 0 to 1 and back to 0) to reset the FIFO. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers. The AD9142A SPI software and the spectrum analyzer should look like Figure |
<WRAP center> | <WRAP center> | ||
| {{ : | | {{ : | ||
- | | Figure | + | | Figure |
</ | </ | ||
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<WRAP center> | <WRAP center> | ||
| {{ : | | {{ : | ||
- | | Figure | + | | Figure |
</ | </ | ||
===== SPI SOFTWARE ===== | ===== SPI SOFTWARE ===== | ||
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<WRAP center> | <WRAP center> | ||
| {{ : | | {{ : | ||
- | | Figure | + | | Figure |
</ | </ | ||
==== PLL ==== | ==== PLL ==== | ||
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<WRAP center> | <WRAP center> | ||
| {{ : | | {{ : | ||
- | | Figure | + | | Figure |
</ | </ | ||
===== EVB Jumper Configurations ===== | ===== EVB Jumper Configurations ===== | ||
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Note: When viewing the modulator output, a local oscillator (LO) must be connected to J15 (”LO_IN”) to properly modulate the signals | Note: When viewing the modulator output, a local oscillator (LO) must be connected to J15 (”LO_IN”) to properly modulate the signals | ||
+ | |||
+ | ===== ACE Software ===== | ||
+ | The ACE software is organized to allow the user to evaluate and control the AD9122A evaluation board. The “Initial Configuration” wizard, which is only available for certain boards, controls the DAC and PLL setups. Block diagram views of the board and chip contain elements that can be used to vary parameters like ref current and data format. These parameters can be changed using check boxes, drop down menus, and input boxes. Some parameters do not have settings shown in the diagram. Double click on the parameter to view the available settings, seen with the NCO settings below. | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | In addition, some parameters can be enabled or disabled. This feature is evident by the color of the block parameter. For example, if the block parameter is dark blue, the parameter is enabled. If it is light grey, it is disabled. To enable or disable a parameter, click on it. | ||
+ | |||
+ | <WRAP column 40%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP column 55%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP column 40%> | ||
+ | <WRAP centeralign> | ||
+ | </ | ||
+ | <WRAP column 55%> | ||
+ | <WRAP centeralign> | ||
+ | </ | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | |||
+ | More direct changes to registers and bit fields can be made in the memory map, which is linked from the chip block diagram through the “Proceed to Memory Map” button. In this view, names, addresses, and data can be manually altered by the user. | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | ACE also contains the Macro Tool, which can be used to record register reads and writes. This is executed in the memory map view or with the initialization wizard. To use, check the “Record Sub-Commands” checkbox and press the record button. Changes in the memory map, which are bolded until they are applied to the part, are recorded as UI commands by the macro tool once the changes are made. Changed register write commands for the controls are also recorded. Hit “Apply Changes” to execute the commands and make changes in the memory map. To stop recording, click the “Stop Recording” button. A macro tool page with the command steps will be created. The macro can be saved using the “Save Macro” button so that it may be loaded for future use. | ||
+ | |||
+ | {{ : | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | The raw macro file will be saved using ACE syntax, which is not easily readable. To remedy this, the ACE software download includes the Macro to Hex Conversion Tool. The user can choose to include or exclude register write, reads, and/or comments in the conversion. The file pathways for the source and save paths should be the same, except that one should be an .acemacro file and the other should be a .txt file. The “Convert” button converts and opens the converted text file, which is easier to read. The conversion tool can also convert back to an .acemacro file if desired. | ||
+ | |||
+ | <WRAP column 40%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP column 55%> | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | <WRAP column 40%> | ||
+ | <WRAP centeralign> | ||
+ | </ | ||
+ | <WRAP column 55%> | ||
+ | <WRAP centeralign> | ||
+ | </ | ||
+ | <WRAP clear> | ||
+ | </ | ||
+ | For more information about ACE and its features, visit https:// | ||
+ |