The AD9139-EBZ connects to a DPG2/3 for quick evaluation of the AD9139, a high-speed, signal processing Digital to Analog Converter. The DPG2/3 automatically formats the data and sends it to the AD9139-EBZ, simplifying evaluation of the device. The Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, REFCLK and DPG2/3 input clock. Figure 2 is an image of the top side of the AD9139-EBZ.
The AD9139 Evaluation Board software has an easy-to-use graphical user interface (GUI). It is included on the Evaluation Board CD, or can be downloaded from the DPG website at http://www.analog.com/dpg. This will install DPGDownloader (for generating and loading vectors into the DPG2/3) and AD9139 SPI software.
Connect +5.0V to P5, GND to P6. One low phase noise high frequency clock source should be connected to the SMA connector, J1 (AD9516_CLKIN). The other low phase noise high frequency clock source should be connected to the SMA connector. The evaluation board connects to the DPG2/3 through the connectors P1 and P2. The PC should be connected to the EVB using the mini-USB connector XP2 after installation of the Evaluation Board software. Figure 1 shows the block diagram of the set-up.
The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http://www.analog.com/dpg. The installation will include the DPG Downloader software as well as all the necessary AD9139 files including schematic, board layout, datasheet, AD9139 SPI, and other files.
1. Install the DPG Downloader and AD9139 SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings.
2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB.
3. Connect the DGP2/3 unit to your PC and turn on the unit.
These settings configure the AD9139 to output a sine wave using the DPG2/3 and allow the user to view the single-tone performance, under the condition: Fdata = 600MHz, 2X interpolation, DAC_output = 60MHz
1. To begin, open the AD9139 SPI application (Start > All Programs > Analog Devices > SPIPro). The screen should look similar to Figure 3.
2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1200MHz, and the output level to 0dBm. The spectrum analyzer can be configured with Start = 20 MHz, Stop = 600 MHz, and Resolution Bandwidth of 3 kHz. Choose Input Attenuation to be -20dB. This can be adjusted later if indications are that the analyzer is causing degradations.
3. Follow the sequence below to configure the AD9139 SPI registers.
a. Click “Reset DAC” button on the “Quick Start” tab.
b. Click “Restore Registers from File” and select the configuration file “AD9139 2X.csv”. This will configure the registers with correct values under the condition we are testing.
c. Click “AD9516 Update” button. This step updates the clock distribution chip AD9516 with the settings that were loaded from the configuration file.
d. There may be a few registers highlighted in red. The red highlights mean mismatches between the SPI read and write values in the software. Clicking “Read All Registers” reads back all the current values in the registers, which should resolve the highlights.
e. Toggle register “FIFO SPI RESET REQUEST”. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers.
f. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9139, as indicated in the “Evaluation Board” drop-down list, and select it. For this evaluation board, LVDS is the only valid Port Configuration, and it will be selected automatically. The “DCO Frequency” window should show the correct data rate (300 MHz). The actual detected frequency may not be exactly 300 MHz but it should be stable and very close to it as shown in Figure 4.
g. Click on “Add Generated Waveform”, and then “Single Tone”. As shown in Figure 5, A Single Tone panel will be added to the vector list. Enter the sample rate, in this case 600 MHz and the desired frequency is 60MHz. Enter the digital amplitude. In this case we use -10dBFS. Check the “Unsigned Data” box. Select the data vector .
h. Click Download () and Play ().
i. Go back to the AD9139 SPI software and toggle the “FIFO SPI RESET REQUEST” button (from 0 to 1 and back to 0) to reset the FIFO. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers. The AD9139 SPI software and the spectrum analyzer should look like Figure 6 and Figure 7 respectively.
4. The current on the 5V supply should read about 940mA.
The AD9139 SPI software is conveniently organized in a series of tabs that groups registers according to their functions. In this way, all registers associated with the digital functions, for example, are on the “Digital Functions” tab. All registers associated with the PLL are on the “PLL” tab, and so on. Normally the “Quick Start” tab is sufficient for a quick evaluation. The most frequently used register controls are included on this tab. A full description of each register and its settings is given in the AD9139 data sheet. Some of the registers and their functions are described here as they pertain to the AD9139 evaluation board. Please note that some of the screen images in this document may not match exactly with the latest revision of the software, due to ongoing improvements and enhancements to the software.
The full screen layout is shown in Figure 5. The tabs can be seen across the top of the work area, and four function buttons in the menu area. “Save Registers to File” and “Restore Registers from File” allow the user to save the current register settings into a file for later uses. A register is immediately updated when the value in the control is changed. Switching between tabs does not update register values. “Read All Registers” can be used to monitor a resister with changing readback values. “ Record Sequence” allows the user to record a series of SPI writes in a particular order and to play back the sequence later. A short description of the register is shown in the status bar on the bottom of the work area when the mouse curser hovers over the control. Some of the tabs are discussed below.
The “Quick Start” tab has selections that apply to the general configuration of the DAC. Reset DAC is recommended every time when the DAC is powered on or reset. Interpolation Rate allows the user to select among the 2 interpolation modes (1X, 2X). According the interface rate selection, if the DLL is necessary to have, then enable the DLL and set the DLL phase. If the FIFO SPI Reset Request sets the FIFO with the requested value through a SPI command. The FIFO Level Read Back should reflect the actual FIFO level after the FIFO SPI Reset Request. Note loading/reloading a vector in the DPG Downloader may generate glitches on the DCI so it is also recommended to toggle the FIFO SPI RESET REQUEST to ensure the FIFO level stays optimal. DCI Clk Div Ratio changes the divide ratio of the AD9516 input clock frequency over DCI frequency. the AD9516 registers in this SPI software are not immediately updated after a user changes the value in a control. AD9516 Update loads the changes in the AD9516 settings.
The “PLL” tab includes all the PLL control registers. The recommended settings for the best performance is PLL Charge Pump Current = 7 and PLL LOOP BW = 7. The user needs to follow the sequence below to enable the PLL.
1. Choose the desired divide ratios in the Loop Divider and the VCO Divider.
2. Set PLL Charge Pump Current and PLL Loop BW settings to 7.
3. Set the PLL Mode to Manual.
4. Turn on PLL Enable.
5. Set the PLL Mode to Auto.
This AD9139 evaluation board is compatible with AD9142-M5375 EBZ, The modulator and one DAC output channel components are not populated.
|Output Viewed||SMA Connector||Jumper Configurations|
|DAC Output||J3(“DAC Output”)||JP6 & JP17 Pins 1-2 (outer pads), JP7 & JP18 Pins 2-3 (inner pads)|
Note: The blue points on the figure10&11 are the jumpers.