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| resources:eval:dpg:ad9122-ebz [14 Jun 2022 05:18] – Draft Deferson Romero | resources:eval:dpg:ad9122-ebz [23 Jan 2024 07:33] (current) – Minor typo error: JP7 changed to JP17 John Marco Mina |
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| ======EVALUATING THE AD9121/AD9122/AD9125 DIGITAL-TO-ANALOG CONVERTER====== | ======EVALUATING THE AD9121/AD9122/AD9125 DIGITAL-TO-ANALOG CONVERTER====== |
| =====Preface===== | =====Preface===== |
| This user guide describes both the hardware and software setup needed to acquire data capture from [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9121.html#eb-overview|AD9121-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9122.html#eb-overview|AD9122-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9125.html|AD9125-M5375-EBZ]] evaluation board to characterize [[adi>media/en/technical-documentation/data-sheets/AD9121.pdf|AD9121]] 14-bit/[[adi>media/en/technical-documentation/data-sheets/AD9122.pdf|AD9122]] 16-bit, Dual, 1.23GSPS, TxDAC+® digital-to-analog converter or [[adi>static/imported-files/data_sheets/AD9125.pdf|AD9125]] 16-bit, Dual, 1GSPS, TxDAC+® digital-to-analog converter. This guide shows how AD9121-M5375-EBZ, AD9122-M5375-EBZ, and AD9125-M5375-EBZ works with ADS7-V2/SDP-H1 controller board developed by Analog Devices. Link to the previous user guide document is provided for customers who still have the DPG2 controller board. | This user guide describes both the hardware and software setup needed to acquire data capture from [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9121.html#eb-overview|AD9121-M5372-EBZ/AD9121-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9122.html#eb-overview|AD9122-M5372-EBZ/AD9122-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9125.html|AD9125-M5372-EBZ/AD9125-M5375-EBZ]] evaluation board to characterize [[adi>media/en/technical-documentation/data-sheets/AD9121.pdf|AD9121]] 14-bit / [[adi>media/en/technical-documentation/data-sheets/AD9122.pdf|AD9122]] 16-bit, Dual, 1.23GSPS, TxDAC+® digital-to-analog converter or [[adi>static/imported-files/data_sheets/AD9125.pdf|AD9125]] 16-bit, Dual, 1GSPS, TxDAC+® digital-to-analog converter. This guide shows how AD9121-M5375-EBZ, AD9122-M5375-EBZ, and AD9125-M5375-EBZ works with ADS7-V2/SDP-H1 controller board developed by Analog Devices. Link to the previous user guide document is provided for customers who still have the DPG2 controller board. |
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| | This guide shows how AD9121 and AD9122 Evaluation boards works with ADS7-V2/SDP-H1 controller board and how AD9125 evaluation board works with SDP-H1 controller board |
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| =====Typical Setup===== | =====Typical Setup===== |
| <WRAP centeralign>{{ :resources:eval:dpg:ad9122_sdp.jpg?600 |}}//Figure 1a. AD9121-M5375-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ with SDP-H1 Setup//</WRAP> | <WRAP centeralign>{{ :resources:eval:dpg:ad9122_sdp.jpg?600 |}}//Figure 1a. AD9121-M5372-EBZ/AD9121-M5375-EBZ/AD9122-M5372-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ with SDP-H1 Setup//</WRAP> |
| <WRAP centeralign>{{ :resources:eval:dpg:ad9122_ads.jpg?600 |}}//Figure 1b. AD9121-M5375-EBZ/AD9122-M5375-EBZ with ADVS7-V2EBZ Setup//</WRAP> | <WRAP centeralign>{{ :resources:eval:dpg:ad9122_ads.jpg?600 |}}//Figure 1b. AD9121-M5372-EBZ/AD9121-M5375-EBZ/AD9122-M5372-EBZ/AD9122-M5375-EBZ with ADVS7-V2EBZ Setup//</WRAP> |
| <note tip>Tip: Click on any picture in this guide to open an enlarged version.</note> | <note tip>Tip: Click on any picture in this guide to open an enlarged version.</note> |
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| =====Quick Start Guide===== | =====Quick Start Guide===== |
| ====Jumpers for Selecting the DAC Output==== | ====Jumpers for Selecting the DAC Output==== |
| Jumpers JP4, JP5, JP6, and JP17 select the output configuration. By default, the DAC output connected to the LPF and the ADL537x analog quadrature modulator. The modulator LO input can be sourced through SMA connector J15 (LO_IN) with clock level at **3dBm**. For selecting DAC output configuration, refer to Table 1 and Figure 2. | Jumpers JP4, JP5, JP6, and JP17 select the output configuration. By default, the DAC output connected to the LPF and the ADL537x analog quadrature modulator. For selecting DAC output configuration, refer to Table 1 and Figure 2. |
| <WRAP >//Table 1. Jumper Configurations for Viewing DAC Output and Modulator Output//</WRAP> | <WRAP >//Table 1. Jumper Configurations for Viewing DAC Output and Modulator Output//</WRAP> |
| ^Output Viewed ^SMA Output ^Jumper Configuration^ | ^Output Viewed ^SMA Output ^Jumper Configuration^ |
| |DAC Output|J3 (DAC1_P) or J8 (DAC1_P)|JP4 and JP5 Pin 2 to Pin 3 (outer pads), JP6 and JP7 Pin 2 to Pin 3 (outer pads)| | |DAC Output|J3 (DAC1_P) or J8 (DAC2_P)|JP4 and JP5 Pin 2 to Pin 3 (outer pads), JP6 and JP17 Pin 2 to Pin 3 (outer pads)| |
| |Modulator Output (Default)|J6 (MOD_OUT)|JP4 and JP5 Pin 1 to Pin 2 (inner pads), JP6 and JP7 Pin 1 to Pin 2 (inner pads)| | |Modulator Output (Default)|J6 (MOD_OUT)|JP4 and JP5 Pin 1 to Pin 2 (inner pads), JP6 and JP17 Pin 1 to Pin 2 (inner pads)| |
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| |{{:resources:eval:dpg:ad9122_dac_output_config.png? }}|{{ :resources:eval:dpg:ad9122_modulator_output_config.png?|}}| | |{{:resources:eval:dpg:ad9122_dac_output_config.png? }}|{{ :resources:eval:dpg:ad9122_modulator_output_config.png?|}}| |
| ===External Power Supply=== | ===External Power Supply=== |
| To implement external supply configuration, remove the header shunt of six pin jumpers, as shown in Figure 4. Refer to Table 2 for external supply jumper connection. | To implement external supply configuration, remove the header shunt of six pin jumpers, as shown in Figure 4. Refer to Table 2 for external supply jumper connection. |
| | <WRAP centeralign>{{ :resources:eval:dpg:ad9122_7_jumpers_-_copy_2_.jpg?600 |}}</WRAP><WRAP centeralign>//Figure 4. AD9122-M5375-EBZ Pin Jumpers//</WRAP> |
| <WRAP >//Table 2. Jumper Configurations for External Power Supply//</WRAP> | <WRAP >//Table 2. Jumper Configurations for External Power Supply//</WRAP> |
| ^Supply Rail ^Remove Jx Pin Jumper ^Apply External Supply^ | ^Supply Rail ^Remove Jx Pin Jumper ^Apply External Supply^ |
| |XCVDD33|JP9|J10| | |XCVDD33|JP9|J10| |
| |AVDD5|JP11|TP11(+5V), TP12 (GND)| | |AVDD5|JP11|TP11(+5V), TP12 (GND)| |
| <WRAP centeralign>{{ :resources:eval:dpg:ad9122_7_jumpers_-_copy_2_.jpg?600 |}}</WRAP><WRAP centeralign>//Figure 4. AD9122-M5375-EBZ Pin Jumpers//</WRAP> | ====Jumper for Selecting Clock Configuration==== |
| | The AD9121-M5372-EBZ/AD9121-M5375-EBZ/AD9122-M5372-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ evaluates both the DAC outputs as well as the AQM outputs. Refer to Table 3 for clock configuration. |
| | <WRAP >//Table 3. Clock Configuration//</WRAP> |
| | ^Output Viewed ^Clock Input ^Local Oscillator Input^ |
| | |DAC Output|J1 (CLKIN)| | |
| | |Modulator Output (Default)|J1 (CLKIN)|J9 (LO_IN)| |
| | The modulator LO input can be sourced through SMA connector J9 (LO_IN) with clock level at **3dBm**. |
| ====Evaluation Guide==== | ====Evaluation Guide==== |
| - Make sure that on AD9121-M5375-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ, JP4, JP5, JP6, and JP17 are configured such that DAC output are connected with J3 (DAC1_P) or J8 (DAC2_P). Refer to Figure 2. | - Make sure that on AD9121-M5375-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ, JP4, JP5, JP6, and JP17 are configured such that DAC output are connected with J3 (DAC1_P) or J8 (DAC2_P). Refer to Figure 2. |
| - Follow evaluation setup in Figure 1a and 1b. | - Follow evaluation setup in Figure 1a and 1b. **AD9121/AD9122** are both compatible with **ADS7/V2EBZ** and **SDP-H1** controller board while **AD9125** is only compatible with **SDP-H1** controller board. |
| * Attach the evaluation board to SDP-H1/ADS7-V2EBZ connector using the AD-DAC-FMC-ADP adapter board. | * Attach the evaluation board to SDP-H1/ADS7-V2EBZ connector using the AD-DAC-FMC-ADP adapter board. |
| * Connect continuous wave generator for clock input to J1. | * Connect continuous wave generator for clock input to J1. |
| * Connect the evaluation board to PC via USB and to a 5Vdc power supply via banana plug cables. | * Connect the evaluation board to PC via USB and to a 5Vdc power supply via banana plug cables. |
| * Connect SDP-H1/ADS7-V2EBZ to PC via USB and to a 12Vdc power supply. | * Connect SDP-H1/ADS7-V2EBZ to PC via USB and to a 12Vdc power supply. |
| * Set clock input to **500MHz** and **2dBm**. | * Set clock input/continuous wave generator to **500MHz** and **2dBm**. |
| - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9121/AD9122/AD9125 evaluation board. Double click this board then modify the configuration, as shown in Figure 5, and click "Apply".<WRAP centeralign>{{ :resources:eval:dpg:ad9122_2_initial_config.jpg?300 |}}//Figure 5. ACE Initial Configuration Wizard when using SDP-H1/ADS7-V2EBZ//</WRAP> | - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9121/AD9122/AD9125 evaluation board. Double click this board then modify the configuration, as shown in Figure 5, and click "Apply".<WRAP centeralign>{{ :resources:eval:dpg:ad9122_2_initial_config.jpg?300 |}}//Figure 5. ACE Initial Configuration Wizard when using SDP-H1/ADS7-V2EBZ//</WRAP> |
| - Open the DPGDownloaderLite. The Evaluation Board **AD9122/AD9122/AD9125**, Controller Board **SDP-H1/ADS7-V2** and DCO Frequency of around **250MHz** will be automatically detected by the DPG downloader. | - Open the DPGDownloaderLite. The evaluation board, controller board and DCO Frequency of around **250MHz** will be automatically recognized by DPG. |
| - In DPGDownloaderLite, **Add Generator Waveforms** pulldown menu select Single Tone and apply the settings as shown in Figure 6. Set the **Data Rate** to 250MHz and **Desired Frequency** to 29 MHz. Set **DAC Resolution** to the DAC’s number of bits to: **14 bits** for AD9121; **16 bits** for AD9122/AD9125. Check the “Generate Complex Data (I & Q)” box and “Unsigned Data” box. | * If using AD9121 / AD9122 with **SDP-H1**, select **LVDS** as port configuration. |
| - Select the in-phase tone from the **I Data Vector** pulldown menu and the quadrature tone from the **Q Data Vector** pulldown menu.<WRAP centeralign>{{ :resources:eval:dpg:ad9122_4_dpg.jpg |}}//Figure 6. DPGDownloader Waveform Configuration for AD9122-M5375-EBZ//</WRAP> | * If using AD9125 with **SDP-H1**, select **LVCMOS-1.8V**as port configuration. |
| - Press the download arrow and then the play button. The spectrum similar to Figure 7 should appear in the signal/spectrum analyzer. <WRAP centeralign>{{ :resources:eval:dpg:ad9122_5_output.png?600 |}}//Figure 7. AD9122-M5375-EBZ FFT for Fdac=500MHz,2x Interpolation Fout=29MHz//</WRAP> | * If using AD9121 / AD9122 with **ADS7-V2EBZ**, use default configuration.<WRAP centeralign>{{ :resources:eval:dpg:sph_port_configuration.jpg?600 |}}//Figure 6. AD9121/AD9122 SDP-H1 Port Configuration / AD9125 SDP-H1 Port Configuration//</WRAP> |
| | - In DPGDownloaderLite, **Add Generator Waveforms** pulldown menu select Single Tone and apply the settings as shown in Figure 7. Set the **Data Rate** to 250MHz and **Desired Frequency** to 29 MHz. Set **DAC Resolution** to the DAC’s number of bits to: **14 bits** for AD9121; **16 bits** for AD9122/AD9125. Check the “Generate Complex Data (I & Q)” box and “Unsigned Data” box. |
| | - Select the in-phase tone from the **I Data Vector** pulldown menu and the quadrature tone from the **Q Data Vector** pulldown menu.<WRAP centeralign>{{ :resources:eval:dpg:ad9122_4_dpg.jpg |}}//Figure 7. DPGDownloader Waveform Configuration for AD9122-M5375-EBZ//</WRAP> |
| | - Press the download arrow and then the play button. The spectrum similar to Figure 8 should appear in the signal/spectrum analyzer. <WRAP centeralign>{{ :resources:eval:dpg:ad9122_5_output.png?600 |}}//Figure 8. AD9122-M5375-EBZ FFT for Fdac=500MHz,2x Interpolation Fout=29MHz//</WRAP> |
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