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resources:eval:dpg:ad9122-ebz [23 Oct 2017 17:38] – [Hardware Setup] Janet Dephoureresources:eval:dpg:ad9122-ebz [23 Jan 2024 07:33] (current) – Minor typo error: JP7 changed to JP17 John Marco Mina
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-====== AD9122 Evaluation Board Quick Start Guide ====== +======EVALUATING THE AD9121/AD9122/AD9125 DIGITAL-TO-ANALOG CONVERTER====== 
-===== Getting Started with the AD9122 Evaluation Board ===== +=====Preface===== 
-==== What's in the Box ==== +This user guide describes both the hardware and software setup needed to acquire data capture from [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9121.html#eb-overview|AD9121-M5372-EBZ/AD9121-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9122.html#eb-overview|AD9122-M5372-EBZ/AD9122-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9125.html|AD9125-M5372-EBZ/AD9125-M5375-EBZ]] evaluation board to characterize [[adi>media/en/technical-documentation/data-sheets/AD9121.pdf|AD9121]] 14-bit / [[adi>media/en/technical-documentation/data-sheets/AD9122.pdf|AD9122]] 16-bit, Dual, 1.23GSPS, TxDAC+® digital-to-analog converter or [[adi>static/imported-files/data_sheets/AD9125.pdf|AD9125]] 16-bit, Dual, 1GSPS, TxDAC+® digital-to-analog converter. This guide shows how AD9121-M5375-EBZ, AD9122-M5375-EBZ, and AD9125-M5375-EBZ works with ADS7-V2/SDP-H1 controller board developed by Analog Devices. Link to the previous user guide document is provided for customers who still have the DPG2 controller board.
-  * AD9122-M5375-EBZ or AD9122-M5372-EBZ Evaluation Board  +
-  * Mini-USB Cable  +
-  * AD9122 Evaluation Board CD +
-==== Recommended Equipment ==== +
-  * Digital Pattern Generator Series 2 or 3 (DPG): ADI HSC-DAC-DPG-BZ OR System Demonstration Platform( SDP-H1) and FMC to High-Speed DAC Evaluation Board Adaptor(AD-DAC-FMC-ADP) +
-  * +5Vdc Power Supply Ex: Agilent E3630A +
-  * DAC Clock Source Ex: Rohde Schwarz SML 02  +
-  * AQM LO Clock Source Ex: Rohde Schwarz SMA100A  +
-  * Spectrum Analyzer Ex: Agilent PSAA or Rohde Schwarz FSU  +
-  * PC: Windows PC with 2 or more USB ports +
-==== Introduction ==== +
-The AD9122 Evaluation Board connects to the Analog Devices Digital Pattern Generator (DPG) or System Demonstration Platform (SDP-H1, PN: EVAL-SDP-CH1Z) to allow for quick evaluation of the AD9122. The DPG or SDP-H1 allows the user to create many types of digital vectors and transmit these at speed to the AD9122 in any of the AD9122 operating modes. The AD9122 evaluation board is configured over USB with accompanying PC software. +
-==== Software Installation ==== +
-The DAC Software Suite plus AD9122 Update should be installed on the PC prior to connecting the hardware to the PC. The DAC Software Suite is included on the Evaluation Board CD, or can be downloaded from the DPG web site at https://wiki.analog.com/resources/eval/dpg/dacsoftwaresuite. This will install DPGDownloader (for loading vectors into the DPG2) and the AD9122 SPI Controller application. However, ACE, a newer evaluation software from ADI, is the preferred evaluation software over the legacy SPI control graphical user interface (GUI). ACE can be downloaded from the ACE website at www.analog.com/ace. The ACE plug-in for the evaluation board, which is also required, is available for download on the AD9122 eval webpage in the software section at http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9122.html#eb-relatedsoftware.  +
-==== Hardware Setup ==== +
-Once the DPGDownloader software is installed, the hardware can be connected as shown below. A single 5V power supply powers the evaluation board. The power supply should be able to source up to 2A to cover all of the board’s operating conditions. A low jitter clock source (< 0.5psec RMS) should be used for the DACCLK. A sinusoidal clock output level of 0 to 4dBm is optimal. By default, the DAC outputs are connected to SMA connectors for evaluation. Both DAC outputs are available. Later in the document, the modifications for observing the modulator output and different clocking options will be shown. +
-  * The evaluation board plugs directly into the DPG2 or DPG3. +
-The PC connects to both the DPG2 and the evaluation board through USB cables as showing in Figure 1 and Figure 2  +
-  * The evaluation boards plugs into the AD-DAC-FMC-ADP adapter board that plugs into the SDP-H1. +
-The PC connects to both the SDP-H1 and the evaluation board through USB cables as shown in Figure 3 and Figure 4.+
  
-{{ :resources:eval:dpg:pics-000.jpg?400 |}} +This guide shows how AD9121 and AD9122 Evaluation boards works with ADS7-V2/SDP-H1 controller board and how AD9125 evaluation board works with SDP-H1 controller board
-Figure 1. DPG2 and AD9122 Evaluation Board Bench set-up +
-{{ :resources:eval:dpg:pics-001.jpg?400 |}} +
-Figure 2. DPG2 and AD9122 Evaluation Board  +
-{{ :resources:eval:dpg:sdph1-ad9747-1.png?300 |}} +
-Figure 3. SDP-H1 and AD9122 Evaluation Board Bench set-up +
-{{ :resources:eval:dpg:sdph1-ad9747-2.png?300 |}} +
-Figure 4. SDP-H1 and AD9122 Evaluation Board +
  
-=====  BASIC HARDWARE SETUP ===== +=====Typical Setup===== 
-Connect the equipment to the AD9122 evaluation board per the following table: +<WRAP centeralign>{{ :resources:eval:dpg:ad9122_sdp.jpg?600 |}}//Figure 1a. AD9121-M5372-EBZ/AD9121-M5375-EBZ/AD9122-M5372-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ with SDP-H1 Setup//</WRAP> 
-  * Equipment Connects to AD9122 Eval Board +<WRAP centeralign>{{ :resources:eval:dpg:ad9122_ads.jpg?600 |}}//Figure 1b. AD9121-M5372-EBZ/AD9121-M5375-EBZ/AD9122-M5372-EBZ/AD9122-M5375-EBZ with ADVS7-V2EBZ Setup//</WRAP> 
-  * Power Supply P5(+5V), P6(GND) +<note tip>Tip: Click on any picture in this guide to open an enlarged version.</note>
-  * Signal Source J1(CLOCK IN), Set source to 500MHz, 2dBm output +
-  * PC USB Cable XP2 +
-  * Spectrum Analyzer J3 (DAC1_P) or J8 (DAC2_P) +
-  * DPG2 P1 and P2 +
-  * SDP-H1 J4(FMC connector)+
  
 +=====Helpful Files:=====
 +  * {{ :resources:eval:dpg:ad9122_userguide.pdf |AD9121 User Guide / AD9122 User Guide}} / {{ :resources:eval:dpg:ad9125_evaluation_board_quick_start_guide.pdf |AD9125 User Guide}} for DPG2/3 users
 +  * Datasheet: [[adi>media/en/technical-documentation/data-sheets/AD9121.pdf|AD9121]] / [[adi>media/en/technical-documentation/data-sheets/AD9122.pdf|AD9122]] / [[adi>static/imported-files/data_sheets/AD9125.pdf|AD9125]]
 +  * IBIS Model: [[adi>en/license/ibis-models?mediaPath=media/en/simulation-models/ibis-models/ad9122.ibs&modelType=ibis-models|AD9121 / AD9122]] / [[adi>Analog_Root/static/techSupport/designTools/ibisModels/license/ibis_general.html?ibs=ad9125.ibs|AD9125]]
 +  * Schematics: {{ :resources:eval:dpg:ad9122-m5372-ebz_rev_a.pdf |AD9122-M5372-EBZ REV A}} / {{ :resources:eval:dpg:ad9122-m5372-ebz_rev_b.pdf |AD9122-M5372-EBZREV B}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_rev_e.pdf |AD9122-M5375-EBZ REV E}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_rev_f.pdf |AD9122-M5375-EBZ REV F}} / {{ :resources:eval:dpg:ad9125-m5372-ebz_revb_schematic.pdf |AD9125-M5372-EBZ REV B}} / {{ :resources:eval:dpg:ad9125-m5375-ebz_revc_schematic.pdf |AD9125-M5375-EBZ REV C}}
 +  * Bill of Materials: {{ :resources:eval:dpg:ad9122-m5372-ebz_reva_bom_customer.xls |AD9122-M5372-EBZ REV A}} / {{ :resources:eval:dpg:ad9122-m5372-ebz_revb_bom_customer.xls |AD9122-M5372-EBZ REV B}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_reve_bom_customer.xls |AD9122-M5375-EBZ REV E}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_revf_bom_customer.xls |AD9122-M5375-EBZ REV F}} / {{ :resources:eval:dpg:ad9125-m5372-ebz_revb_bom_customer.xls |AD9125-M5372-EBZ REV B}} / {{ :resources:eval:dpg:ad9125-m5375-ebz_revc_bom_customer.xls |AD9125-M5375-EBZ REV C}}
 +  * PCB Gerber Files: {{ :resources:eval:dpg:ad9122-m5372-ebz_reva_gerber_files.zip |AD9122-M5372-EBZ REV A}} / {{ :resources:eval:dpg:ad9122-m5372-ebz_revb_gerber_files.zip |AD9122-M5372-EBZ REV B}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_reve_gerber_files.zip |AD9122-M5375-EBZ REV E}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_revf_gerber_files.zip |AD9122-M5375-EBZ REV F}} / {{ :resources:eval:dpg:ad9125-m5375-ebz_revc_gerber_files.zip |AD9125-M5375-EBZ REV C}}
 +  * PCB Board Files: {{ :resources:eval:dpg:ad9122-m5372-ebz_reva.zip |AD9122-M5372-EBZ REV A}} / {{ :resources:eval:dpg:ad9122-m5372-ebz_revb.zip |AD9122-M5372-EBZ REV B}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_reve.zip |AD9122-M5375-EBZ REV E}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_revf.zip |AD9122-M5375-EBZ REV F}} / {{ :resources:eval:dpg:ad9125-m5372-ebz_revb.zip |AD9125-M5372-EBZ REV B}} / {{ :resources:eval:dpg:ad9125-m5375-ebz_revc.zip |AD9125-M5372-EBZ REV C}}
 +  * PCB Layout: {{ :resources:eval:dpg:ad9122-m5372-ebz_reva_layout.pdf |AD9122-M5372-EBZ REV A}} / {{ :resources:eval:dpg:ad9122-m5372-ebz_revb_layout.pdf |AD9122-M5372-EBZ REV B}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_reve_layout.pdf |AD9122-M5375-EBZ REV E}} / {{ :resources:eval:dpg:ad9122-m5375-ebz_revf_layout.pdf |AD9122-M5375-EBZ REV F}} / {{ :resources:eval:dpg:ad9125-m5375-ebz_revc_layout.pdf |AD9125-M5375-EBZ REV C}}
 +=====Software Needed:=====
 +  * [[:resources:tools-software:ace|Analysis | Control | Evaluation (ACE) Software]]
 +  * [[:resources:tools-software:ace:dpg-lite|DPG Lite]] (installed with ACE)
 +<note important>Do not install ACE on a computer with DAC Software Suite.</note>
 +
 +=====Hardware Needed:=====
 +  * [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9121.html#eb-overview|AD9121-M5372-EBZ/AD9121-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9122.html#eb-overview|AD9122-M5372-EBZ/AD9122-M5375-EBZ]] / [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9125.html|AD9125-M5372-EBZ/AD9125-M5375-EBZ]] Evaluation Board
 +  * [[:resources:eval:dpg:hsdac-sdp-h1|SDP-H1]] (EVAL-SDP-CH1Z) Evaluation Kit / [[:resources:eval:ads7-v2|ADS7-V2EBZ]] Evaluation Kit
 +  * [[adi>AD-DAC-FMC]]-ADP High-Speed DAC Evaluation Board to FMC Adaptor Board
 +  * PC with ACE and DPG Lite Software Applications
 +  * 5Vdc Power Supply
 +  * (2) Banana Plug Cables
 +  * High-Frequency Continuous Wave Generator
 +  * Signal/Spectrum Analyzer
 +  * USB-A to USB-Mini Cable
 +  * (2) SMA Cables
 +  * The following are included in SDP-H1 Evaluation Kit:
 +    * 12Vdc Wall Adapter
 +    * USB-A to USB-Mini Cable
 +  * The following are included in ADS7-V2 Evaluation Kit:
 +    * 12Vdc Power Supply
 +    * Power Cord
 +    * USB-A to USB-B Cable
  
-===== Getting Started ===== +=====Quick Start Guide===== 
-It is suggested that the basic set-up is verified before making any modifications to the evaluation board.+====Jumpers for Selecting the DAC Output==== 
 +Jumpers JP4, JP5, JP6, and JP17 select the output configuration. By default, the DAC output connected to the LPF and the ADL537x analog quadrature modulator. For selecting DAC output configuration, refer to Table 1 and Figure 2. 
 +<WRAP >//Table 1. Jumper Configurations for Viewing DAC Output and Modulator Output//</WRAP>  
 +^Output Viewed ^SMA Output ^Jumper Configuration^ 
 +|DAC Output|J3 (DAC1_P) or J8 (DAC2_P)|JP4 and JP5 Pin 2 to Pin 3 (outer pads), JP6 and JP17 Pin 2 to Pin 3 (outer pads)| 
 +|Modulator Output (Default)|J6 (MOD_OUT)|JP4 and JP5 Pin 1 to Pin 2 (inner pads), JP6 and JP17 Pin 1 to Pin 2 (inner pads)|
  
-==== Generating a Test Vector with ACE ==== +|{{:resources:eval:dpg:ad9122_dac_output_config.png? }}|{{ :resources:eval:dpg:ad9122_modulator_output_config.png?|}}|
-1. Power up the DPG and connect the USB cable to the PC.\\ \\ +
-2. Next, run the DPGDownloader Software. To launch DPGDownloader,, click Start > Programs > Analog Devices > DPG > DPGDownloader. If the AD9122 evaluation board has been recognized by the PC, AD9122 should be populated in the Evaluation Board field in the Hardware Config panel.\\ \\ +
-3. Generate a sine wave by pulling down the “Add Generated Waveform” menu and choosing “Single Tone”. Fill in the form as shown below (Sample Rate = 250MHz, Desired Frequency = 29 MHz, etc.). Note that the Sample Rate should match the input sample rate and not the DAC update rate.\\ \\ +
-{{ :resources:eval:dpg:dpgdownloader9122.png?640 }} \\ +
-4. Select the I and Q data vectors in the data selection panel.\\ \\ +
-5. Hit the download button. This transfers the data from the PC to the DPG memory.\\ \\ +
-6. When the vector has finished downloading, hit the play button. This starts the DPG2 transmitting data to the eval board.\\ \\ +
-7. Open ACE from the start window. It can be found by following the file path to the program or by searching in the windows search bar for “ACE.” The {{:resources:eval:user-guides:ace_icon_small.png}} icon indicates the ACE software.\\ \\ +
-8. If the board is connected properly, ACE will detect it and display it on the Start page under "Attached Hardware." Double click this board.\\ \\ +
-{{ :resources:eval:user-guides:ad9122_detected.png }} \\ +
-9. Ensure that the {{:resources:eval:user-guides:connection_icon.png}} button is green in the subsystem image under the “System” tab. If not, click it, select the AD9122, and click "Acquire." Double click on the subsystem image.\\ \\ +
-{{ :resources:eval:user-guides:ad9122_system.png }} \\ +
-10. To the left of the board diagram, click "Modify" under "Initial Configuration Summary" to edit the DAC and PLL setup of the board. In some cases, the "Initial Configuration" page will already be shown.\\ \\ +
-{{ :resources:eval:user-guides:ad9122_boardview.png }} \\ +
-11. Alter the inputs to match the figure below. Click "Apply."\\ \\ +
-{{ :resources:eval:user-guides:ad9122_applypage_new.png }} \\ +
-12. Double click on the dark blue AD9122 on the board diagram. Ensure that the settings of the AD9122 match with the chip diagram in the figure below and click "Apply Changes." The "Poll Devices" button and PLL Locked should both be enabled. If neither are enabled, click "Read All" or reset the board, reset the chip, and reapply the settings for the board and chip. For more information about ACE, see the "ACE Software Features" section.\\ \\ +
-{{ :resources:eval:user-guides:ad9122_chipview.png }} \\ +
-13. The output from J7 and J8 should be a clean 29MHz tone as shown below: +
-{{ :resources:eval:dpg:29_mhz_spectrum.png?400 }} +
- +
-==== Generating a Test Vector with the SPI Controller ==== +
-Launch the AD9122 SPI GUI by clicking the AD9122 SPI button. +
-1. Power up the DPG and connect the USB cable to the PC.\\ \\ +
-2. Next, run the DPGDownloader Software. To launch DPGDownloader,, click Start > Programs > Analog Devices > DPG > DPGDownloader. If the AD9122 evaluation board has been recognized by the PC, AD9122 should be populated in the Evaluation Board field in the Hardware Config panel.\\ \\ +
-3. Generate a sine wave by pulling down the “Add Generated Waveform” menu and choosing “Single Tone”. Fill in the form as shown below (Sample Rate = 250MHz, Desired Frequency = 29 MHz, etc.). Note that the Sample Rate should match the input sample rate and not the DAC update rate.\\ \\ +
-{{ :resources:eval:dpg:dpgdownloader9122.png?640 }} \\ +
-4. Select the I and Q data vectors in the data selection panel.\\ \\ +
-5. Launch the AD9122 SPI GUI by clicking the AD9122 SPI button.\\ \\ +
-6. Go to the “Data Clock” tab and change the Interpolation field to “2x”.\\ \\ +
-7. When the Run button is clicked, the SPI controller will run once. It will both write and read from the AD9122/AD9125 and setup the clock chip (AD9516) on the evaluation board. The Run Forever control will continue to read from the chip and will update the SPI when any of the controls change. The Force Write and Read Only controls force the controller to write all the controls to the evaluation board or only read from the SPI port.\\ \\ +
-8. The DCO frequency field in the DPGDownloader window should now be reading something close to 250MHz.\\ \\ +
-9. Hit the download button. This transfers the data from the PC to the DPG memory.\\ \\ +
-10. When the vector has finished downloading, hit the play button. This starts the DPG2 transmitting data to the eval board.\\ \\ +
-11. The output from J7 and J8 should be a clean 29MHz tone as shown below: +
-{{ :resources:eval:dpg:29_mhz_spectrum.png?400 }} +
- +
-===== AD9122 SPI Controller ===== +
-{{ :resources:eval:dpg:pics-003.jpg?400|}} The SPI Controller application is split into several tabs. These tabs group related functions. Several of the functions provided by the SPI Controller are described here, as they relate to the evaluation board. For complete descriptions of each register, refer to the AD9122 datasheet. In the interest of continuous quality improvements, the images below may not exactly match your version of the software. +
- +
-==== Data Clock Control ==== +
-This section, shown to the right, provides control over the Interpolation Rate and Course Modulation. Once the controller is executed, the Modulation Description field will return a summary of control. If an improper selection is made, the field will return ‘Invalid.’ The DATAFMT field selects the number format of the incoming data, between unsigned (Binary) and signed (2’s compliment). The QFirst control selects which DAC receives data first from the interleaved bus. For use with the DPG2, this should always be set to IQ Pairs. The Interface Mode selects how wide the data bus will be. This setting will need to match the setting in the DPG AD9122 panel for proper operation with the DPG2. +
-==== NCO Control ==== +
-This tab controls the Fine Modulation within the AD9122. The top portion of this tab helps the user easily control the frequency shift. It will calculate the NCO Frequency using Data Frequency entered by the user. The NCO can shift the signal by at most +/- fnco/2. An indicator also displays the frequency shift from the course modulation on the previous tab. The total shift will be the sum of the course and fine modulations. To manually enter the Frequency Tuning Word (FTW), the Enable Advanced Control will bypass the calculations on the top of the page. +
-==== PLL Control ==== +
-The AD9122 has an on-chip PLL. When PLL_ENABLE is turned on, the chip will automatically select the appropriate band using the Divder1 and Divider0 values. This tab provides the calculation for the DAC Freq and VCO Freq based on the Reference Clock and the value of the dividers. The VCO Frequency must be between 1 and 2 GHz for proper operation. The auto-band select can be bypassed by enabling PLL MANUAL and entering a band in PLL Band Select. Divider1 and Divider0 must still be chosen appropriately in this mode of operation. +
-==== Interrupts ==== +
-This tab provides a visual indication of the state of each interrupt. Enabling the button to the left of each interrupt with enable the interrupt. A green indicator to the right of the button will light when the interrupt is asserted. Once asserted, the interrupt can be acknowledged by pressing the Clear button. +
-==== Main DAC Control ==== +
-This tab controls the two main DACs in the AD9122. The Full-Scale Current of each DAC can be set with the I DAC Gain and Q DAC Gain controls. The I Sleep and Q Sleep controls put their respective DAC into a low-power sleep state. When the AD9122 is used with a modulator, the Phase Compensation/DC Offset controls can be used to correct any mismatches between the two DACs. +
-===== Filter Tool ===== +
-A filter tool that helps users determine the AD9122 interpolation filter is best suited for their application can be launched by clicking the “Filter Tool” Button on the DPGDownloader main window. The figure to the right shows the user interface. +
-{{ :resources:eval:dpg:9122_filter_tool.png?720 }} +
-===== Selecting the DAC Outputs ===== +
-By default, solder jumpers JP4, JP5, JP6, and JP17 configure the AQM output to be observed at SMA output J6. This connects the DAC outputs to the LPF and the ADL537x analog quadrature modulator. The modulator LO input can be sourced through SMA connector J15 (LO_IN). The clock level into the modulator should be set to about 3 dBm. In order to observe the DAC outputs at Jumpers J3 and J8, the solder jumpers need to be repositioned as shown below. +
- +
-|{{:resources:eval:dpg:dac_output_config.png? }}|{{ :resources:eval:dpg:modualtor_output_config.png?|}}|+
 |  DAC Output Configuration  |  Modulator Output Configuration  | |  DAC Output Configuration  |  Modulator Output Configuration  |
- +<WRAP centeralign>//Figure 2. AD9121-M5375-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ Output Configuration//</WRAP> 
-===== Jumper Options ===== +====Jumper for Selecting Power Supply==== 
-There are 7 pin jumpers on the evaluation board. The pin jumpers are corresponding to the 6 supplies on the board. They serve as ‘switches’ that determine if the LDOs on board or external supplies are used for each individual supply. They are shunted by default, which means on board LDOs are used. When an external supply is necessary, pull off the shunt from the corresponding supply and connect the external supply to the SMA jack close to the jumper. The seventh pin jumper configures the voltage of the IOVDD supply. +The evaluation board has a provision for on board or external power supply configuration. 
-^Supply Rail ^For LDO, Install Pin Jumper ^For external Supply, use SMA^ +===Internal Power Supply=== 
-|CVDD18|     JP2|                         J4| +On board power supply is implemented by default using LDO.  
-|DVDD18|     JP3|                         J11| +**JP1** selects the supply voltage level for IOVDD. Refer to Figure 3. 
-|IOVDD|      JP12|                        J12| +  * When Pin 1 and Pin 2 are connected, IOVDD = 3.3 V (Default) 
-|AVDD33|     JP8|                         J13| +  * When Pin 2 and Pin 3 are connected, IOVDD = 1.8 V <WRAP centeralign>{{ :resources:eval:dpg:ad9122_iovdd.jpg?400 |}}</WRAP><WRAP centeralign>//Figure 3. AD9122-M5375-EBZ IOVDD//</WRAP> 
-|XCVDD33|    JP9|                         J10| +===External Power Supply=== 
-|AVDD5|      JP11|                        TP11(+5V), TP12 (GND)| +To implement external supply configuration, remove the header shunt of six pin jumpers, as shown in Figure 4. Refer to Table 2 for external supply jumper connection. 
- +<WRAP centeralign>{{ :resources:eval:dpg:ad9122_7_jumpers_-_copy_2_.jpg?600 |}}</WRAP><WRAP centeralign>//Figure 4. AD9122-M5375-EBZ Pin Jumpers//</WRAP> 
-===== ACE Software Features ===== +<WRAP >//Table 2. Jumper Configurations for External Power Supply//</WRAP>  
-The ACE software is organized to allow the user to evaluate and control the AD9122A evaluation board. The “Initial Configuration” wizard, which is only available for certain boards, controls the DAC and PLL setups. Block diagram views of the board and chip contain elements that can be used to vary parameters like ref current and data format. These parameters can be changed using check boxes, drop down menus, and input boxes. Some parameters do not have settings shown in the diagram. Double click on the parameter to view the available settings, seen with the NCO settings below.  +^Supply Rail ^Remove Jx Pin Jumper ^Apply External Supply^ 
- +|CVDD18|JP2|J4| 
-{{ :resources:eval:user-guides:ad9122_nco.png }} +|DVDD18|JP3|J11| 
-<WRAP clear> +|IOVDD|JP12|J12| 
-</WRAP> +|AVDD33|JP8|J13| 
-<WRAP centeralign> NCO settings for the AD9122 </WRAP> +|XCVDD33|JP9|J10| 
- +|AVDD5|JP11|TP11(+5V), TP12 (GND)| 
-In addition, some parameters can be enabled or disabled. This feature is evident by the color of the block parameter. For example, if the block parameter is dark blue, the parameter is enabled. If it is light grey, it is disabled. To enable or disable a parameter, click on it.  +====Jumper for Selecting Clock Configuration==== 
- +The AD9121-M5372-EBZ/AD9121-M5375-EBZ/AD9122-M5372-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ evaluates both the DAC outputs as well as the AQM outputs. Refer to Table 3 for clock configuration. 
-<WRAP column 40%> +<WRAP >//Table 3. Clock Configuration//</WRAP>  
-{{ :resources:eval:user-guides:ad9739a_on.png }} +^Output Viewed ^Clock Input ^Local Oscillator Input^ 
-</WRAP> +|DAC Output|J1 (CLKIN)| | 
-<WRAP column 55%> +|Modulator Output (Default)|J1 (CLKIN)|J9 (LO_IN)| 
-{{ :resources:eval:user-guides:ad9739a_off.png }} +The modulator LO input can be sourced through SMA connector J9 (LO_IN) with clock level at **3dBm**. 
-</WRAP> +====Evaluation Guide==== 
-<WRAP clear> +  - Make sure that on AD9121-M5375-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ, JP4, JP5, JP6, and JP17 are configured such that DAC output are connected with  J3 (DAC1_P) or J8 (DAC2_P). Refer to Figure 2. 
-</WRAP> +  - Follow evaluation setup in Figure 1a and 1b. **AD9121/AD9122** are both compatible with **ADS7/V2EBZ** and **SDP-H1** controller board while **AD9125** is only compatible with **SDP-H1** controller board. 
-<WRAP column 40%> +     * Attach the evaluation board to SDP-H1/ADS7-V2EBZ connector using the AD-DAC-FMC-ADP adapter board. 
-<WRAP centeralign> Enabled parameter </WRAP> +     * Connect continuous wave generator for clock input to J1. 
-</WRAP> +     * Connect the DAC output from J3 (DAC1_P) or J8 (DAC2_P) to a signal/spectrum analyzer. 
-<WRAP column 55%> +     * Connect the evaluation board to PC via USB and to a 5Vdc power supply via banana plug cables. 
-<WRAP centeralign> Disabled parameter </WRAP> +     * Connect SDP-H1/ADS7-V2EBZ to PC via USB and to a 12Vdc power supply. 
-</WRAP> +     * Set clock input/continuous wave generator to **500MHz** and **2dBm**. 
-<WRAP clear> +  - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9121/AD9122/AD9125 evaluation board. Double click this board then modify the configuration, as shown in Figure 5, and click "Apply".<WRAP centeralign>{{ :resources:eval:dpg:ad9122_2_initial_config.jpg?300 |}}//Figure 5. ACE Initial Configuration Wizard when using SDP-H1/ADS7-V2EBZ//</WRAP> 
-</WRAP> +  - Open the DPGDownloaderLite. The evaluation board, controller board and  DCO Frequency of around **250MHz** will be automatically recognized by DPG. 
- +     * If using AD9121 / AD9122 with **SDP-H1**, select **LVDS** as port configuration.  
-More direct changes to registers and bit fields can be made in the memory map, which is linked from the chip block diagram through the “Proceed to Memory Map” button. In this view, names, addresses, and data can be manually altered by the user.  +     * If using AD9125 with **SDP-H1**, select **LVCMOS-1.8V**as port configuration. 
- +     * If using AD9121 / AD9122 with **ADS7-V2EBZ**, use default configuration.<WRAP centeralign>{{ :resources:eval:dpg:sph_port_configuration.jpg?600 |}}//Figure 6. AD9121/AD9122 SDP-H1 Port Configuration / AD9125 SDP-H1 Port Configuration//</WRAP> 
-{{ :resources:eval:user-guides:ad9122_memmap.png }} +  - In DPGDownloaderLite, **Add Generator Waveforms** pulldown menu select Single Tone and apply the settings as shown in Figure 7. Set the **Data Rate** to 250MHz and **Desired Frequency** to 29 MHz. Set **DAC Resolution** to the DAC’s number of bits to: **14 bits** for AD9121; **16 bits** for AD9122/AD9125. Check the “Generate Complex Data (I & Q)” box and “Unsigned Data” box. 
-<WRAP clear> +  - Select the in-phase tone from the **I Data Vector** pulldown menu and the quadrature tone from the **Q Data Vector** pulldown menu.<WRAP centeralign>{{ :resources:eval:dpg:ad9122_4_dpg.jpg |}}//Figure 7. DPGDownloader Waveform Configuration for AD9122-M5375-EBZ//</WRAP> 
-</WRAP> +  - Press the download arrow and then the play button. The spectrum similar to Figure 8 should appear in the signal/spectrum analyzer. <WRAP centeralign>{{ :resources:eval:dpg:ad9122_5_output.png?600 |}}//Figure 8. AD9122-M5375-EBZ FFT for Fdac=500MHz,2x Interpolation Fout=29MHz//</WRAP>
-<WRAP centeralign> Bench Set-Up </WRAP> +
- +
-ACE also contains the Macro Tool, which can be used to record register reads and writes. This is executed in the memory map view or with the initialization wizard. To use, check the “Record Sub-Commands” checkbox and press the record button. Changes in the memory map, which are bolded until they are applied to the part, are recorded as UI commands by the macro tool once the changes are made. Changed register write commands for the controls are also recorded. Hit “Apply Changes” to execute the commands and make changes in the memory map. To stop recording, click the “Stop Recording” button. A macro tool page with the command steps will be created. The macro can be saved using the “Save Macro” button so that it may be loaded for future use.  +
- +
-{{ :resources:eval:user-guides:ad9122_macrocommands.png }} +
-<WRAP clear> +
-</WRAP> +
-<WRAP centeralign> Macro tool in ACE. The //Stop Recording//, //Record//, and //Save Macro// commands are located at the top of the macro tool. </WRAP> +
- +
-The raw macro file will be saved using ACE syntax, which is not easily readable. To remedy this, the ACE software download includes the Macro to Hex Conversion Tool. The user can choose to include or exclude register write, reads, and/or comments in the conversion. The file pathways for the source and save paths should be the same, except that one should be an .acemacro file and the other should be a .txt file. The “Convert” button converts and opens the converted text file, which is easier to read. The conversion tool can also convert back to an .acemacro file if desired.  +
- +
-<WRAP column 40%> +
-{{ :resources:eval:user-guides:ad9122_m2hconvert_5.png }} +
-</WRAP> +
-<WRAP column 55%> +
-{{ :resources:eval:user-guides:ad9122_m2hconvert_4.png }} +
-</WRAP> +
-<WRAP clear> +
-</WRAP> +
-<WRAP column 40%> +
-<WRAP centeralign> Conversion set-up for macro to hex </WRAP> +
-</WRAP> +
-<WRAP column 55%> +
-<WRAP centeralign> Converted text file </WRAP> +
-</WRAP> +
-<WRAP clear> +
-</WRAP> +
-For more information about ACE and its features, visit https://wiki.analog.com/resources/tools-software/ace.+
  
resources/eval/dpg/ad9122-ebz.1508773092.txt.gz · Last modified: 23 Oct 2017 17:38 by Janet Dephoure

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