This version (22 Aug 2023 21:02) was approved by Brad Hall.
Table of Contents
Transmitter Signal Chain Overview and Theory of Operation
Link to higher level page: Space Based Satcom Reference Design
The overall TX block diagram is shown below. The wiki sections below will walk through the design elements of each sub-circuit.
Digital to Analog Converter (DAC) + DSP
The AD9082 (“MxFE”) is an ideal digitizer for this wideband RF front end due to its high level of integration, performance, and RF sampling rate. The MxFE’s high instantaneous and analog input bandwidth enable RF sampling up to 8GHz, providing architectural and frequency planning flexibility at the system level. It also has highly configurable, on-chip DSP capabilities (DDC/DUC channelizers, NCOs, and programmable FIR filters) as well as four DAC channels and two ADCs for use in this multi-channel system.
The ADF4371 integrated PLL/VCO is an ideal choice for generating the MxFE sample clock. The ADF4371 can generate a clean, low-jitter clock from 62.5MHz up to 32GHz, and its differential outputs are capable of directly driving the MxFE clock pins. The ADF4371 is also used to generate clocking for the LO signal. You can read more about the LO signal path here.
The LTC6953 clock distributor is used to ensure proper clock synchronization between all of the ADF4371's throughout this reference design. An external source generates a clock signal, which is then buffered and replicated before being sent to the FPGA, the AD9082, and both the TX and RX LO signal paths.
Although only a single LTC6953 is required for 4T4R, With EZSync™ or ParallelSync™, multichip synchronization is realizable, allowing for expandability while maintaining the proper clock signals.
Up-converter Design
By utilizing a high performance ADRF5022 silicon switch, the down-converter design allows for two separate signal paths to achieve wideband capability. The high frequency X, Ku and Ka-band signals pas through the ADRF5022's switch state “2” and are applied to the IF input of the ADMFM2001. Before mixing with an external LO, the signals pass through a cascaded chain inside the SIP involving a lowpass filter, power amplifier, a second lowpass filter, and attenuator. The signals are then applied to the ADMFM2001's internal mixer where they are up converted to an RF by mixing with an external LO. For more information about LO generation for this particular design, see this link. The high frequency RF signals are then amplified by HMC7950 before further signal conditioning. C, S, L, and UHF band signals bypass the ADMFM2001 SIP and are sent to the beamforming section after further RF conditioning.
TX Beamforming Network and PA
The 4T4R beamforming network consists of a modular array of four BFIC tiles, allowing for sixteen elements. The transmit path for multi-beam analog beamforming begins with a Knowles BPF followed by an ADAR5000. The BFP removed unwanted spurs just outside our desired band. The ADAR5000 Wilkinson splitter divides each of the four channels into four equal phase constituents, for a total of 16 subchannels for each of the four BFIC tiles. The signals enter the ADAR3000 where their individual amplitude and phase can be manipulated via the variable amplitude and phase blocks (VAPS). After the ADAR3000, more filtering and amplification is performed before the signal is transmitted via the antenna.
Timing and Control
Automatic gain control (AGC), RF path switching, and beam switching/reconfiguration often have critical timing specs that drive component selection, especially in systems that require fast frequency hopping or wideband tuning. The RF switches, DSAs, and tunable beam states in the transmitter signal chain offer fast switching and settling times, a high degree of configurability, and can be controlled via standard parallel and/or SPI interfaces. The tables below list the control interfaces and minimum configuration and settling time details at the component level for each of the sections of this reference design.
TX Beamforming Network
Inside of the ADAR3000-CSL, there are 16 digital step attenuators and 16 time delay units (TDU) combined into Variable Amplitude and Phase (VAP) blocks. Each digital step attenuator provides up to 31.5dB of attenuation with a resolution of 0.5dB. Each TDU can provide up to 54.5 ps of delay in steps of 0.865 ps. Each of the VAPs can tuned in a minimum of 10ns.
The ADAR3000-CSL contains internal RAM which can store up to 64 states for each beam for a total of 256 beam states. For faster access, there is also optional FIFO memory, which stores up to 16 beam states per channel for a total of 64 beam states. The ADAR3000-CSL is conveniently controlled by 4-wire SPI, allowing for control of up to 16 devices on the same serial line.
TX Performance Simulations and Measurements
Wideband Signal Conditioning Only
The following simulations were created using Keysight SystemVue/Genesys. All components in the TX signal chain were modeled with frequency-dependent sys-parameter or s-parameter datasets to ensure accurate simulation results. The signal chain below takes into account the following components:
- Manufacturer-provided, frequency-dependent s-parameter or sys-parameter datasets for every active and passive RF component
- A standalone model of the ADMFM2001 microwave downconverter containing signal chains each with their own frequency-dependent s-parameter or sys-parameter datasets
- A standalone model of an AD9082 DAC containing frequency-dependent sys-parameter datasets
- Frequency-dependent component interconnect modeling i.e. PCB trace loss approximation for DC-50GHz CPWG traces, 30mil Rogers 4350 PCB stackup
The Genesys workspace incorporates various system level cascade analyses that takes advantage of MATLAB equation-based frequency planning. Three different analyses are shown below:
- Noise power Spectral Simulation
- Two-Tone Test Spectral Simulation
- System Cascade highlighting gain (CGAIN), noise figure (CNF), third order output intercept (EOIP3), output 1dB compression point (EOP1DB), minimum detectable signal (MDS), and carrier to noise distortion ratio (CNDR)
Noise Power Spectral Simulation
Two-Tone Test Spectral Simulation
System Cascade
As mentioned above, the system cascade simulation measures gain (CGAIN), noise figure (CNF), third order output intercept (EOIP3), output 1dB compression point (EOP1DB), minimum detectable signal (MDS), and carrier to noise distortion ratio (CNDR). The x-axis shows all of the individual components cascaded together and the nodes in between. The variables are shown on two separate y axes for scaling purposes. The markers are placed on “Node 8” which is the end of the signal chain, before the beamforming section.
Beamforming Front End Only
The following simulations were created using Keysight SystemVue/Genesys. All components in the TX signal chain were modeled with frequency-dependent sys-parameter or s-parameter datasets to ensure accurate simulation results. The signal chain below takes into account the following components:
- Manufacturer-provided, frequency-dependent s-parameter or sys-parameter datasets for every active and passive RF component
- A standalone model of the ADMFM2001 microwave downconverter containing signal chains each with their own frequency-dependent s-parameter or sys-parameter datasets
- A standalone model of an AD9082 DAC containing frequency-dependent sys-parameter datasets
- Frequency-dependent component interconnect modeling i.e. PCB trace loss approximation for DC-50GHz CPWG traces, 30mil Rogers 4350 PCB stackup
The Genesys workspace incorporates various system level cascade analyses that takes advantage of MATLAB equation-based frequency planning. Three different analyses are shown below:
- Noise power Spectral Simulation
- Two-Tone Test Spectral Simulation
- System Cascade highlighting gain (CGAIN), noise figure (CNF), third order output intercept (EOIP3), output 1dB compression point (EOP1DB), minimum detectable signal (MDS), and carrier to noise distortion ratio (CNDR)
Noise Power Spectral Simulation
Two-Tone Test Spectral Simulation
System Cascade
As mentioned above, the system cascade simulation measures gain (CGAIN), noise figure (CNF), third order output intercept (EOIP3), output 1dB compression point (EOP1DB), minimum detectable signal (MDS), and carrier to noise distortion ratio (CNDR). The x-axis shows all of the individual components cascaded together and the nodes in between. The variables are shown on two separate y axes for scaling purposes. The markers are placed on “Node xx” which is the end of the signal chain, before the beamforming section.
Wideband Signal Conditioning and Beamforming Combined
The following simulations were created using Keysight SystemVue/Genesys. All components in the TX signal chain were modeled with frequency-dependent sys-parameter or s-parameter datasets to ensure accurate simulation results. The signal chain below takes into account the following components:
- Manufacturer-provided, frequency-dependent s-parameter or sys-parameter datasets for every active and passive RF component
- A standalone model of the ADMFM2001 microwave downconverter containing signal chains each with their own frequency-dependent s-parameter or sys-parameter datasets
- A standalone model of an AD9082 DAC containing frequency-dependent sys-parameter datasets
- Frequency-dependent component interconnect modeling i.e. PCB trace loss approximation for DC-50GHz CPWG traces, 30mil Rogers 4350 PCB stackup
The Genesys workspace incorporates various system level cascade analyses that takes advantage of MATLAB equation-based frequency planning. Three different analyses are shown below:
- Noise power Spectral Simulation
- Two-Tone Test Spectral Simulation
- System Cascade highlighting gain (CGAIN), noise figure (CNF), third order output intercept (EOIP3), output 1dB compression point (EOP1DB), minimum detectable signal (MDS), and carrier to noise distortion ratio (CNDR)
Noise Power Spectral Simulation
Two-Tone Test Spectral Simulation
System Cascade
As mentioned above, the system cascade simulation measures gain (CGAIN), noise figure (CNF), third order output intercept (EOIP3), output 1dB compression point (EOP1DB), minimum detectable signal (MDS), and carrier to noise distortion ratio (CNDR). The x-axis shows all of the individual components cascaded together and the nodes in between. The variables are shown on two separate y axes for scaling purposes. The markers are placed on “Node 2” which is the end of the signal chain, before the signal is sent to antenna.
TX Chain Bill of Materials
The table below lists the part numbers for the components used in the RX path. Where space qualified parts are not available, the commercial part number is listed. Some of the part numbers listed below are space specials which do not appear on analog.com. Please contact ADI sales or an authorized distributor for more information and to receive orderable part numbers.
| Device | Description | Package | Process | Qualification Level | Production Status | |||||
| ADRF5730 | 0.1 to 40 GHz Digital Step Attenuator | 24-Terminal LGA | Advanced Silicon | TBD | Recommended for New Designs | |||||
| ADRF5022 | 0.1 GHz to 44 GHz Silicon SPDT Reflective Switch | 12-Lead LGA | Advanced Silicon | AQEC-Standard | Recommended for New Designs | |||||
| ADRF5144 | 1 GHz to 20 GHz Silicon SPDT Reflective Switch | 20-Terminal LGA | Silicon | TBD | Recommended for New Designs | |||||
| HMC8413 | Low Noise Amplifier, 0.01 GHz to 9 GHz | 6-Lead LFCSP | GaAs pHEMPT | TBD | Recommended for New Designs | |||||
| HMC7950 | Low Noise Amplifier, 2 GHz to 28 GHz | 16-Lead LCC | GaAs pHEMPT | TBD | Recommended for New Designs | |||||
| AD9082 | MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC | 324-Ball BGA | - | TBD | Recommended for New Designs | |||||
| ADAR3000 | 17 GHz to 22 GHz, 4-Beam and 4-Element, Ka-Band Beamformer SIP | 311-ball CSPBGA | - | TBD | Recommended for New Designs | |||||
| ADAR5000 | 4-Way RF Splitter Combiner, 17 GHz to 32 GHz | WLCSP | - | TBD | Recommended for New Designs | |||||
| ADMFM2001 | 7 GHz to 31 GHz Microwave Up Converter SIP | 179-Pin BGA | - | TBD | Pre-Release | |||||
| LFCG-4400+ | Mini Circuits LTCC Low Pass Filter, DC - 4400 MHz | package | GaAs Integrated Passive Component | Contact Mini Circuits | Recommended for New Designs | |||||
| L204XF4S | Knowles DLI 20.4 GHz Surface Mount Low Pass Filter | package | GaAs Integrated Passive Component | Contact Knowles DLI | Recommended for New Designs | |||||
| B192NB2S | Knowles DLI 19.2 GHz Surface Mount Band Pass Filter | package | GaAs Integrated Passive Component | Contact Knowles DLI | Recommended for New Designs | |||||
| BFHK-1982+ | Mini Circuits LTCC Band Pass Filter, 17500 - 22200 MHz | package | GaAs Integrated Passive Component | Contact Mini Circuits | Recommended for New Designs | |||||
resources/eval/developer-kits/space-based-satcom-ref-design/tx-overview.txt · Last modified: 27 Jul 2023 14:52 by Connor Bryant