The two large, polarized capacitors placed close to the VDD terminal act up as a close-by charge reservoir when a voltage source with long cables is being utilized. For most applications, these large caps would not be necessary.
The amount of capacitance needed is function of numerous factors:
DO NOT HOT PLUG THE VDD POWER SOURCE !
To power-up the circuit safely via the VDD power socket, it is strongly recommended to follow the steps below.
The bulk capacitors can remain charged for a significant amount of time after power down. To avoid injuries and/or damage to the board , it is important to:
The drain pulse generator comprises of the LTC7000A, a FET and the crowbar circuit (ADP3625 + FET). To pulse the drain, apply a 0-3.3V pulse onto the DRAIN_PULSE_ENABLE SMA connector. The pulse modulates the INP pin of the LTC7000A which, in turn, drives Q1 on and off. A high on DRAIN_PULSE_ENABLE turns on the FET and applies VDD onto the PA drain.
The turn-on time is controlled by the LTC7000A.TGUP signal and the amount of capacitance connected to the PA drain (VDD_PA signal). Too much capacitance on the PA drain rail can not only slow down the turn-on edges but also create large input current spikes on the line. To avoid such issues, it is recommended to keep the total amount of capacitance at the PA drain to less than 10nF.
The LTC7000A.TGDN pin controls the time it takes to turn off Q1. As for the time it takes to transition the PA drain from on to off, it is dependent on the amplifier itself unless the “crowbar circuit” is used. If not used, the “turn-off time” is function of the power amplifier itself. The amplifier acts as a resistive load. As soon as Q1 is off, the PA starts draining the capacitors on the rail. How fast is function of the drain voltage, PA IDD, PA off threshold and a few other parameters. It is preferable to test this behavior with the right PA. For a more predictable turn-off time, it is recommended to use the “crowbar circuit”. As the name implies, the “crowbar circuit” forces a fast discharge of the PA drain voltage by connecting it to ground via a low-resistance switch. Turn off times <1μs can be achieved with the crowbar circuit.
The selection of Q1 and Q2 could be optimized for a certain application type. Various characteristics would need to be consider such as drain voltage/current, max gate voltage, Vgs(th), etc.
The R3 placeholder can be used for evaluation of the drain pulser circuit without connecting a power amplifier. The DC power that can be dissipated from R3 is limited. It is important to operate the circuit in pulsed mode only. It is also recommended to use a pulse proof power resistor.
The PA drain voltage can be monitored via the VDD_PA_SENSE SMA connector (refer to "Drain pulser circuit" ). To measure, the test equipment connected can be terminated to either 50Ω or high-Z with limitations for each.
VVDD_PA_SNS = VVDD_PA × RTERMINATION / (RTERMINATION + R28)
VVDD_PA_SNS = VVDD_PA × 47.6mV/V
There are two means of measuring the PA drain current on this evaluation board.
VIMONP − VIMONN = (IDRAIN × 10mΩ × 200μA/V) × (100kΩ ⁄⁄ R56)
IDRAIN = (VIMONP − VIMONN) × 33A/V
VISNSP − VISNSN = IDRAIN × 10mΩ × 10V/V
IDRAIN = (VISNSP − VISNSN) × 10A/V
For more signal at the ISNSP/N terminals, the gain of the LT1999 can be increased by selecting either the LT1999-20, gain of 20, or LT1999-50), gain of 50. The gain increase comes at the expense of a slower response time.
To improve measurement accuracy, it is preferable to calibrate the current monitoring path. One approach would be to connect an electronic load on VDD_PA and setting the DRAIN_PULSE_ENABLE voltage to 3.3V to turn-on the VDD drain path.
The gain of both current sense paths gain be increased by substituting R9 for a higher value. R9 also controls the current limit of the circuit via the ECB function of the LTC7000A. Hence, it is appropriate to design the ECB first, then the current sense monitor circuit(s).
It is worth noting, neither current sense methods can accurately detect drain current during ON → OFF and OFF → ON transitions when drain pulsing. The current required to transition the VDD power path FET, Q1, is summed to the PA drain current. Only when the FET is fully on or off will the results be precise.
The LTC7000A, in combination with R9 and Q1, has the capability to turn off the VDD power path if the current exceeds 6A typical for about 10-15μs. The circuit will automatically retry to start after a brief cooling period. The resistor off the LTC7000A.ISET pin can be substituted to modify the overcurrent protection threshold. Refer to the LTC7000A datasheet for details. The purpose of diode D1 is to clamp inductive kickbacks that may be seen when the ECB turns off Q1.
There are three key stages to the negative converter:
The series resistance, R32, is present to damp the quality factor of the bead+cap filter
Noise creation and rejection was a key aspect of the component selection. Similarly, various bypass options were included to allow users to better optimize the DC-DC conversion circuit for their use case. As example:
The dual opamps along with the SPST analog switch, ADG1401, form the gate pulse circuit. A logic low at the GATE_PULSE_ENABLE SMA connector forces a voltage equivalent to the desired pinch-off gate voltage at the PA gate signal. A logic 1, 3.3V, sets the PA gate voltage to the desired bias-voltage. And a pulse train on the GATE_PULSE_ENABLE SMA connector would generate pulses at the PA VGG signal between PA on (VBIAS) and PA off (VPINCH_OFF) PA gate voltage thresholds.
Amplifier A1a, ADA4896-2, is used as a buffer/level-shifter amplifier for the pinch-off threshold reference voltage. To set the pinch-off voltage, adjust R42 and R43 per equation:
VPINCH_OFF = VLT3093_VEE * R42 / (R42 + R43)
The eval is set to -5.0V VPINCH_OFF.
The on threshold, VBIAS, is controlled via the resistor divider network R45, R47 and potentiometer R46. It can be estimated using the following equation:
VBIAS = VPINCH_OFF × (R46 ⁄⁄ R47) / (R45 + R46 ⁄⁄ R47)
R46 is a 2k potentiometer. With the -5.0V default pinch-off voltage, the bias voltage can be adjusted over the range [-3.33V, -0.9V]. The upper limit is defined by the input common-mode voltage range of the buffer amplifier.
The ADG1401 state is controlled via the GATE_PULSE_ENABLE SMA connector. A logic 1 connects the resistor divider to ground, generating VBIAS which then is applied to the input of the gate driver amplifier. A logic 0 floats the resistor divider, connecting the output of amplifier A1a to the input of the gate driver and generating VPINCH_OFF.
Amplifier A1b, ADA4896-2, acts up as a buffer/driver between the capacitance that’s located on the PA VGG (VGG1) signal and the pulsed resistor network. The 50Ω output resistance is to help stabilize the buffer amplifier when capacitively loaded.
When drain pulsing, the gate remains at VBIAS. A constant 3.3V can be applied to the GATE_PULSE_ENABLE connector. Another method would be to drive the gate signal directly from the LT3093 output. To do so:
The actual sequencing of the power rails at the PA, drain and gate, are mainly controlled via state of the pulse SMA connectors, GATE_PULSE_ENABLE and DRAIN_PULSE_ENABLE. Despite that fact, the circuit is designed to follow a certain sequence if the two SMA connectors are left floating and power applied on VDD . The sequence is as follow:
The board was setup to facilitate gate pulsing usage by enabling the VDD/drain power path by default. If the preferred method is to keep the PA drain path off on start-up, either set DRAIN_PULSE_ENABLE to a logic 0 or, for a more permanent change, depopulate the pull-up resistor R12 and populate the termination resistor R13 off the INP pin.