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resources:eval:developer-kits:pulser-plus:performanceplots [26 Jan 2024 17:50] – text Eamon Nashresources:eval:developer-kits:pulser-plus:performanceplots [26 Jan 2024 17:58] (current) – Text Eamon Nash
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 +======Performance Plots======
 All measurements were performed with the ADPA1106 evaluation board plugged directly into the Pulser Plus board. To facilitate fast on/off switching when in Gate Pulsed Mode, all of the capacitance on the VGG1 and VGG2 pins was removed except for a 100 pF capacitor on each pin. This configuration was used for both Drain Pulsed Mode and Gate Pulsed Mode. The default capacitors on the VDD1 and VDD2 pins on the evaluation board (1000pF, 390 pF and 100pF with some series resistance) were left in place for operation in Drain Pulsed Mode and Gate Pulsed Mode.  All measurements were performed with the ADPA1106 evaluation board plugged directly into the Pulser Plus board. To facilitate fast on/off switching when in Gate Pulsed Mode, all of the capacitance on the VGG1 and VGG2 pins was removed except for a 100 pF capacitor on each pin. This configuration was used for both Drain Pulsed Mode and Gate Pulsed Mode. The default capacitors on the VDD1 and VDD2 pins on the evaluation board (1000pF, 390 pF and 100pF with some series resistance) were left in place for operation in Drain Pulsed Mode and Gate Pulsed Mode. 
  
resources/eval/developer-kits/pulser-plus/performanceplots.txt · Last modified: 26 Jan 2024 17:58 by Eamon Nash