This version (24 Jan 2023 20:08) was approved by Brad Hall.The Previously approved version (20 Jul 2022 17:05) is available.
Power Architecture Overview
The power solution for the 2-24GHz Front End provides regulation for the three major functional blocks in the system: the transmit chain, the receive chain, and the AD9081 or AD9082 MxFE with clocking solution.
The power for the transmit chain (shown below) features two switching regulators. One is the ultra-small MAXM17632, which delivers 1A at high efficiency from up to 36Vin in a tiny 3x3mm uSLICTM package. The other is the ADP5600, which integrates a low ripple interleaved inverting charge pump with a high performance LDO to easily produce clean negative voltages. The sensitive signal chain power domains are regulated by low noise, high performance linear regulators.
The power for the receive chain (shown below) follows a similar design philosophy as the transmit. It uses the same MAXM17632 power module and highly integrated ADP5600 to minimize the solution space. The sensitive power domains of the signal chain are regulated by low noise linear regulators.
The power solution for the MxFE and its clock (shown below) features Slient Switcher® technology. These high efficiency regulators, LTM8051, LT8625S and LT8627S, feature low EMI and output noise. Some power domains of the MxFE chip can be driven directly from a Silent Switcher output, while the more sensitive ICs such as the ADF4377 clock chip are further regulated by LDOs like the LT3045. The LT3045 LDO features industry leading performance with 77dB PSRR at 1MHz.
To request the complete LTPowerPlanner design files for 2-24Ghz MxFE Front End, please send an email to 2to24_FE_sim_workspace_request [at] analog [dot] com and include the following info:
- Name
- Job Title
- Company Name
- Company Location
- Application/Use Case
resources/eval/developer-kits/2to24ghz-mxfe-rf-front-end/power-architecture.txt · Last modified: 24 Jan 2023 20:08 by Brad Hall