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resources:eval:ad9684-500ebz [23 Sep 2022 09:08] – [Configuring the Board] John Xavier Toledo | resources:eval:ad9684-500ebz [13 Jan 2023 02:42] (current) – [Device Setup - Full Bandwidth Mode] John Xavier Toledo | ||
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- | ====== EVALUATING THE AD9684 | + | ====== EVALUATING THE AD9684 |
===== Preface ===== | ===== Preface ===== | ||
This user guide describes the [[adi> | This user guide describes the [[adi> | ||
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===== Helpful Documents ===== | ===== Helpful Documents ===== | ||
* [[adi> | * [[adi> | ||
- | * HSC-ADC-EVALE evaluation kit ([[hsc-adc-evale|hsc-adc-evale]]) | + | * [[adi> |
* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
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* Analog signal source and antialiasing filter | * Analog signal source and antialiasing filter | ||
* Encode clock source | * Encode clock source | ||
- | * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[hsc-adc-evale|hsc-adc-evale]]) | + | * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[adi> |
* PC running Windows® | * PC running Windows® | ||
* USB 2.0 port | * USB 2.0 port | ||
* [[adi> | * [[adi> | ||
- | * [[hsc-adc-evale|HSC-ADC-EVALEZ]] FPGA-based data capture kit | + | * [[adi> |
===== Getting Started ===== | ===== Getting Started ===== | ||
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==== Configuring the Board ==== | ==== Configuring the Board ==== | ||
Before using the software for testing, configure the evaluation board as follows: | Before using the software for testing, configure the evaluation board as follows: | ||
- | - Connect the evaluation board to the [[hsc-adc-evale|HSC-ADC-EVALEZ]] data capture board, as shown in Figure 2. | + | - Connect the evaluation board to the [[adi> |
- | - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[hsc-adc-evale|HSC-ADC-EVALEZ]] board. Connect the Standard-B USB port of the [[hsc-adc-evale|HSC-ADC-EVALEZ]] board to the PC with the supplied USB cable. | + | - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[adi> |
- | - Turn on the [[hsc-adc-evale|HSC-ADC-EVALEZ]]. | + | - Turn on the [[adi> |
- | - The [[hsc-adc-evale|HSC-ADC-EVALEZ]] will appear in the Windows(R) Device Manager | + | - The [[adi> |
- | - If the Device Manager does not show the [[hsc-adc-evale|HSC-ADC-EVALEZ]] listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | + | - If the Device Manager does not show the [[adi> |
- | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector | + | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector |
- | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J100. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, |
- | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, |
==== Visual Analog Setup ==== | ==== Visual Analog Setup ==== | ||
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- If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 6){{ : | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 6){{ : | ||
- Click the **Settings** button in the **ADC Data Capture** block to view the capture size as shown in Figure 7 {{ : | - Click the **Settings** button in the **ADC Data Capture** block to view the capture size as shown in Figure 7 {{ : | ||
- | - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) per channel. The HSC-EVALE FPGA software supports up to 256K FFT capture (128K per channel){{ : | + | - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) per channel. The [[adi> |
- | - Click on the **Capture Board** tab and browse to the **ad9684_evalez_05202014_0903am.mcs** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the HSC-EVALE board indicating that the FPGA has been correctly programmed. The bin file is available at the ftp site [[ftp:// | + | - Click on the **Capture Board** tab and browse to the **ad9684_evalez_05202014_0903am.mcs** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the [[adi> |
- Click **OK** | - Click **OK** | ||
==== SPIController Setup ==== | ==== SPIController Setup ==== | ||
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- Input Full Scale Range (25): At high input frequencies, | - Input Full Scale Range (25): At high input frequencies, | ||
+ | |||
+ | ==== Device Setup - Full Bandwidth Mode ==== | ||
+ | - The settings in the ADCBase0 tab must be changed to configure the AD9684. In this example, the AD9684 is set up to use **Full Bandwidth Mode** for 2 ADC channels. | ||
+ | |||
+ | |||
+ | ==== Obtaining an FFT - Full Bandwidth Mode ==== | ||
+ | - The first item to configure in Visual Analog is the input clock frequency. | ||
+ | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | ||
+ | - Adjust the amplitude of the input signal so that the fundamental is at the -1.0 dBFS level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) | ||
+ | - To save the FFT plot do the following: | ||
+ | - Click on the Float Form button in the FFT window {{ : | ||
+ | - Click on File < | ||
==== Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ==== Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ||
- | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDCs. In this example the AD9684 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two. Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox. | + | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDCs. In this example the AD9684 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two. Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox. |
- The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated. | - The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated. | ||
- The tuning step is equal to the output sample rate divided by 4096. | - The tuning step is equal to the output sample rate divided by 4096. | ||
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- DDC Phase Increment = 62500000/ | - DDC Phase Increment = 62500000/ | ||
- Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Decimate by 4 Filter Selection (when in real mode this actually sets the AD9684 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Decimate by 4 Filter Selection (when in real mode this actually sets the AD9684 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | ||
- | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | + | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : |
==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ||
- The first item to configure in Visual Analog is the input clock frequency. | - The first item to configure in Visual Analog is the input clock frequency. | ||
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. | ||
- | - To save the FFT plot do the following | + | - To save the FFT plot do the following: |
- | - Click on the Float Form button in the FFT window | + | - Click on the Float Form button in the FFT window {{ : |
- | {{ : | + | - Click on File < |
- | - Click on File < | + | |
==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ||
- | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC. In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked. | + | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC. In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked. |
- The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | - The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | ||
- | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | + | |
==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ||
- | - The first item to configure in Visual Analog is the input clock frequency. | + | - The first item to configure in Visual Analog is the input clock frequency. |
- | - In order to exclude the image frequency from the SFDR measurements, | + | - In order to exclude the image frequency from the SFDR measurements, |
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. | ||
- To save the FFT plot do the following | - To save the FFT plot do the following | ||
- | - Click on the Float Form button in the FFT window{{ : | + | - Click on the Float Form button in the FFT window{{ : |
- | - Click on File < | + | - Click on File < |
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* If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | ||
* In VisualAnalog, | * In VisualAnalog, | ||
- | * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure | + | * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure |
** The FFT plot appears normal, but performance is poor. ** | ** The FFT plot appears normal, but performance is poor. ** | ||
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** The FFT window remains blank after the Run button is clicked ** | ** The FFT window remains blank after the Run button is clicked ** | ||
- | * Make sure the evaluation board is securely connected to the hsc-adc-evale. | + | * Make sure the evaluation board is securely connected to the [[adi> |
- | * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the HSC-EVALE . If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the hsc-adc-evale setup process. | + | * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the [[adi> |
* Make sure the correct FPGA //bin// file was used to program the FPGA. | * Make sure the correct FPGA //bin// file was used to program the FPGA. | ||
* Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, | * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, | ||
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** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ||
- | * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure | + | * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure |