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resources:eval:ad9684-500ebz [26 Feb 2016 20:40] – [AD9684 Evaluation Board] Jonathan Harrisresources:eval:ad9684-500ebz [13 Jan 2023 02:42] (current) – [Device Setup - Full Bandwidth Mode] John Xavier Toledo
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-====== EVALUATING THE AD9684 DUAL 14B ADC ======+====== EVALUATING THE AD9684 ANALOG-TO-DIGITAL CONVERTER ======
 ===== Preface ===== ===== Preface =====
 This user guide describes the [[adi>AD9684|AD9684]] evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described. This user guide describes the [[adi>AD9684|AD9684]] evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described.
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 ===== Typical Measurement Setup ===== ===== Typical Measurement Setup =====
-{{ :eval:ad9684_setupevalez.jpg?direct&600 |}}<WRAP centeralign> +{{ :resources:eval:ad9684_evalez_setup.jpg?direct&600 |}}<WRAP centeralign> 
-//Figure 2. Evaluation Board Connection—[[adi>AD9684|AD9684-500EBZ (on Left) and [[HSC-ADC-EVALEZ|HSC-ADC-EVALEZ]] (on Right)//+//Figure 2. Evaluation Board Connection—[[adi>AD9684|AD9684-500EBZ]] (on Left) and [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] (on Right)//
 </WRAP> </WRAP>
 ===== Features ===== ===== Features =====
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 ===== Helpful Documents ===== ===== Helpful Documents =====
   * [[adi>AD9684|AD9684]] Data Sheet   * [[adi>AD9684|AD9684]] Data Sheet
-  * HSC-ADC-EVALE evaluation kit ([[hsc-adc-evale|hsc-adc-evale]]) +  * [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]], //HSC-ADC-EVALEZ Evaluation Kit//
   * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual//    * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// 
   * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//   * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//
-  * [[>resources/technical-guides/adispi>|ADI SPI Application Note]] // ADI Serial Control Interface Standard//+  * [[adi>an-877|AN-877 Application Note]], //Interface to High-Speed ADCs via SPI//
   * [[adi>an-835|AN-835 Application Note]], //Understanding ADC Testing and Evaluation//   * [[adi>an-835|AN-835 Application Note]], //Understanding ADC Testing and Evaluation//
  
 ===== Software Needed ===== ===== Software Needed =====
-  * VisualAnalog [[ftp://ftp.analog.com/pub/HSSP_SW/VisualAnalog/VisualAnalog_Setup.exe]]    +  * [[adi>en/design-center/interactive-design-tools/visualanalog.html | VisualAnalog]] 
-  * SPIController [[ftp://ftp.analog.com/pub/adispi/A2DComponents/Install/SPIController_Setup.exe]]+  * [[adi>en/design-center/interactive-design-tools/spicontroller.html | SPIController ]]
 ===== Design and Integration Files ===== ===== Design and Integration Files =====
-  * ftp://ftp.analog.com/pub/HSC_ADC_Apps/AD9684CE01A_Design_Support/ +  * Schematic: {{ :resources:eval:ad9684_sch.pdf | AD9684 Rev A}} 
-  * FPGA MCS file [[ftp://ftp.analog.com/pub/HSC_ADC_Apps/AD9684CE01A_Design_Support/ad9684_evalez_05202014_0903am.mcs]]+  * Layout: {{ :resources:eval:ad9684_lay.pdf | AD9684 Rev A}} 
 +  * Bill of Materials: {{ :resources:eval:ad9684_bom.xlsx | AD9684 Rev A}} 
 +  * FPGA MCS file: {{ :resources:eval:ad9684_evalez_05202014_0903am.zip}}
 ===== Equipment Needed ===== ===== Equipment Needed =====
   * Analog signal source and antialiasing filter   * Analog signal source and antialiasing filter
   * Encode clock source    * Encode clock source 
-  * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[hsc-adc-evale|hsc-adc-evale]])+  * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]])
   * PC running Windows®   * PC running Windows®
   * USB 2.0 port   * USB 2.0 port
   * [[adi>AD9684|AD9684-500EBZ]] board   * [[adi>AD9684|AD9684-500EBZ]] board
-  * [[hsc-adc-evale|hsc-adc-evale]] FPGA-based data capture kit+  * [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] FPGA-based data capture kit
  
 ===== Getting Started ===== ===== Getting Started =====
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 ==== Configuring the Board ==== ==== Configuring the Board ====
 Before using the software for testing, configure the evaluation board as follows:  Before using the software for testing, configure the evaluation board as follows: 
-  - Connect the evaluation board to the [[hsc-adc-evale|hsc-adc-evale]] data capture board, as shown in Figure 2. +  - Connect the evaluation board to the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] data capture board, as shown in Figure 2. 
-  - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[hsc-adc-evale|hsc-adc-evale]] board. Connect the Standard-B USB port of the [[hsc-adc-evale|hsc-adc-evale]] board to the PC with the supplied USB cable.  +  - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] board. Connect the Standard-B USB port of the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] board to the PC with the supplied USB cable.  
-  - Turn on the [[hsc-adc-evale|hsc-adc-evale]].  +  - Turn on the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]].  
-  - The [[hsc-adc-evale|hsc-adc-evale]] will appear in the Windows(R) Device Manager +  - The [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] will appear in the Windows(R) Device Manager 
-  - If the Device Manager does not show the [[hsc-adc-evale|hsc-adc-evale]] listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. +  - If the Device Manager does not show the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. 
-  - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock. +  - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J201 and set the amplitude to 14dBm. This is the ADC Sample Clock. 
-  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) +  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J100. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) 
-  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)+  - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
  
 ==== Visual Analog Setup ==== ==== Visual Analog Setup ====
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   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 6){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Figure 6. Expanding Display in VA//</WRAP>   - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 6){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Figure 6. Expanding Display in VA//</WRAP>
   - Click the **Settings** button in the **ADC Data Capture** block to view the capture size as shown in Figure 7 {{ :eval:ad9684_capture_settings.png?400 |}}<WRAP centeralign>//Figure 7. Setting the capture length//</WRAP>   - Click the **Settings** button in the **ADC Data Capture** block to view the capture size as shown in Figure 7 {{ :eval:ad9684_capture_settings.png?400 |}}<WRAP centeralign>//Figure 7. Setting the capture length//</WRAP>
-  - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) per channel. The HSC-EVALE FPGA software supports up to 256K FFT capture (128K per channel){{ :eval:ad9684_500m_capture_settings.png?400 |}}<WRAP centeralign>//Figure 8. Setting the clock frequency //</WRAP> +  - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) per channel. The [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] FPGA software supports up to 256K FFT capture (128K per channel){{ :eval:ad9684_500m_capture_settings.png?400 |}}<WRAP centeralign>//Figure 8. Setting the clock frequency //</WRAP> 
-  - Click on the **Capture Board** tab and browse to the **ad9684_evalez_05202014_0903am.mcs** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the HSC-EVALE board indicating that the FPGA has been correctly programmed. The bin file is available at the ftp site [[ftp://ftp.analog.com/pub/HSC_ADC_Apps/AD9684CE01A_Design_Support/ad9684_evalez_05202014_0903am.mcs]]+  - Click on the **Capture Board** tab and browse to the **ad9684_evalez_05202014_0903am.mcs** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] board indicating that the FPGA has been correctly programmed. The bin file is available at the **Design and Integration Files** section
   - Click **OK**   - Click **OK**
 ==== SPIController Setup ==== ==== SPIController Setup ====
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     - Input Full Scale Range (25): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.      - Input Full Scale Range (25): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.
  
 +
 +==== Device Setup - Full Bandwidth Mode ====
 +  - The settings in the ADCBase0 tab must be changed to configure the AD9684. In this example, the AD9684 is set up to use **Full Bandwidth Mode** for 2 ADC channels.  Set the Chip Application Mode in register 0x200 to **Full Bandwidth Mode**.  Set the Chip Decimation Ratio in register 0x201 to **Full Sample Rate**. Since the chip is configured to Full Bandwidth mode, the DDC configuration is bypassed and the sampling frequency is decimated by 1. {{ :resources:eval:ad9684_full_bw_mode.png?800 |}}<WRAP centeralign>//Figure 11. Set Application Mode to Full Bandwidth Mode//</WRAP>
 +
 +
 +==== Obtaining an FFT - Full Bandwidth Mode ====
 +  - The first item to configure in Visual Analog is the input clock frequency.  This is the frequency of the input clock and NOT the decimated sample rate (if using decimation).  Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.
 +  - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:ad9684_full_bw_mode_fft.png?600 |}}<WRAP centeralign>//Figure 12. AD9684-500 FFT at 170.3 MHz Input signal for Full Bandwidth Mode//</WRAP>
 +  - Adjust the amplitude of the input signal so that the fundamental is at the -1.0 dBFS level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.)
 +  -  To save the FFT plot do the following:
 +      - Click on the Float Form button in the FFT window {{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 13. Floating the FFT window//</WRAP>
 +      - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 14. Saving the FFT//</WRAP>
  
 ==== Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== ==== Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ====
-    - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDCs. In this example the AD9684 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two.  Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox.  Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2ddcrealdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 11. Set Application Mode to 2 DDCs Real Mode Decimate by 2//</WRAP>+    - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDCs. In this example the AD9684 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two.  Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox.  Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2ddcrealdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 15. Set Application Mode to 2 DDCs Real Mode Decimate by 2//</WRAP>
     - The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated.     - The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated.
        - The tuning step is equal to the output sample rate divided by 4096.        - The tuning step is equal to the output sample rate divided by 4096.
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            - DDC Phase Increment = 62500000/122070.3125 = 512            - DDC Phase Increment = 62500000/122070.3125 = 512
     - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Decimate by 4 Filter Selection (when in real mode this actually sets the AD9684 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512     - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Decimate by 4 Filter Selection (when in real mode this actually sets the AD9684 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512
-        - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2ddcrealdec2_adcbase1.png?650 |}}<WRAP centeralign>//Figure 12. Channel A and Channel B DDC Settings//</WRAP>+        - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2ddcrealdec2_adcbase1.png?650 |}}<WRAP centeralign>//Figure 16. Channel A and Channel B DDC Settings//</WRAP>
 ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ====
   - The first item to configure in Visual Analog is the input clock frequency.  This is the frequency of the input clock and NOT the decimated sample rate (if using decimation).  Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.  In addition, the DDC data must be selected under the Output Data section.  DDC0 and DDC1 are being used in the AD9684 so this must be selected under the ADC Data Capture Settings.   - The first item to configure in Visual Analog is the input clock frequency.  This is the frequency of the input clock and NOT the decimated sample rate (if using decimation).  Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.  In addition, the DDC data must be selected under the Output Data section.  DDC0 and DDC1 are being used in the AD9684 so this must be selected under the ADC Data Capture Settings.
-  - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_2ddcrealdec2.png?600 |}}<WRAP centeralign>//Figure 13. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP>+  - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_2ddcrealdec2.png?600 |}}<WRAP centeralign>//Figure 17. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP>
   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range.  A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog.   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range.  A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog.
-  -  To save the FFT plot do the following +  - To save the FFT plot do the following: 
-    - Click on the Float Form button in the FFT window +      - Click on the Float Form button in the FFT window {{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 18. Floating the FFT window//</WRAP> 
-{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 14. Floating the FFT window//</WRAP> +      - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 19. Saving the FFT//</WRAP>
-    - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 15. Saving the FFT//</WRAP>+
 ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ====
-    - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC.   In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two.  Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked.  Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 16. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2//</WRAP>+    - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC.   In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two.  Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked.  Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 20. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2//</WRAP>
     - The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B.     - The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B.
-       - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcbase1.png?400 |}}<WRAP centeralign>//Figure 17. DDC Settings for Complex ZIF Mode//</WRAP>+    - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcbase1.png?400 |}}<WRAP centeralign>//Figure 21. DDC Settings for Complex ZIF Mode//</WRAP>
 ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ====
-  - The first item to configure in Visual Analog is the input clock frequency.  This is the frequency of the input clock and NOT the decimated sample rate (if using decimation).  Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.  In addition, the DDC data must be selected under the Output Data section.  DDC0 is being used in the AD9684 so this must be selected under the ADC Data Capture Settings.{{ :eval:AD9684_2ddcrealdec2_datacapturesettings.png?400 |}}<WRAP centeralign>//Figure 18. AD9684-500 FFT Data Capture Settings//</WRAP> +  - The first item to configure in Visual Analog is the input clock frequency.  This is the frequency of the input clock and NOT the decimated sample rate (if using decimation).  Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.  In addition, the DDC data must be selected under the Output Data section.  DDC0 is being used in the AD9684 so this must be selected under the ADC Data Capture Settings.{{ :eval:AD9684_2ddcrealdec2_datacapturesettings.png?400 |}}<WRAP centeralign>//Figure 22. AD9684-500 FFT Data Capture Settings//</WRAP> 
-  - In order to exclude the image frequency from the SFDR measurements, configure Visual Analog to remove the image from its calculations.  This is done under the FFT Analysis settings.  Under the User-Defined tab add a new row by clicking Add.  Name it ‘Image’.  Use a symbol such as the # and set the Freq to ‘-fund’.  Set the Single-Side Band to 3 Bins and set it as ‘Spur, Exclude’.  Once done, select the row, and then hit the Move Up button to place this new row just below the row with Fund.{{ :resources:eval:AD6674_2adc1ddccomplexdec2_fftanalysissettings.png?700 |}}<WRAP centeralign>//Figure 19. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP> +  - In order to exclude the image frequency from the SFDR measurements, configure Visual Analog to remove the image from its calculations.  This is done under the FFT Analysis settings.  Under the User-Defined tab add a new row by clicking Add.  Name it ‘Image’.  Use a symbol such as the # and set the Freq to ‘-fund’.  Set the Single-Side Band to 3 Bins and set it as ‘Spur, Exclude’.  Once done, select the row, and then hit the Move Up button to place this new row just below the row with Fund.{{ :resources:eval:AD6674_2adc1ddccomplexdec2_fftanalysissettings.png?700 |}}<WRAP centeralign>//Figure 23. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP> 
-  - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_1ddccomplexdec2.png?600 |}}<WRAP centeralign>//Figure 20. AD9684-500 FFT with 1 DDC in Complex ZIF Mode with Dec2 Enabled//</WRAP>+  - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_1ddccomplexdec2.png?600 |}}<WRAP centeralign>//Figure 24. AD9684-500 FFT with 1 DDC in Complex ZIF Mode with Dec2 Enabled//</WRAP>
   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range.  A -1dBFS input signal will show as -2dBFS in Visual Analog.   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range.  A -1dBFS input signal will show as -2dBFS in Visual Analog.
   -  To save the FFT plot do the following   -  To save the FFT plot do the following
-    - Click on the Float Form button in the FFT window{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 21. Floating the FFT window//</WRAP> +    - Click on the Float Form button in the FFT window{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 25. Floating the FFT window//</WRAP> 
-    - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:AD9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 22. Saving the FFT//</WRAP>+    - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:AD9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 26. Saving the FFT//</WRAP>
  
  
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   * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.    * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. 
   * In VisualAnalog, Click on the Settings button in the **Input Formatter** block. Check that **Number Format** is set to the correct encoding (twos compliment by default). Repeat for the other channel.   * In VisualAnalog, Click on the Settings button in the **Input Formatter** block. Check that **Number Format** is set to the correct encoding (twos compliment by default). Repeat for the other channel.
-  * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure 23{{ :eval:AD9684_datapathsoftreset.png?nolink |}}<WRAP centeralign>//Figure 23. Issuing a data path soft reset through SPIController//</WRAP>+  * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure 27{{ :eval:AD9684_datapathsoftreset.png?nolink |}}<WRAP centeralign>//Figure 27. Issuing a data path soft reset through SPIController//</WRAP>
  
 ** The FFT plot appears normal, but performance is poor. ** ** The FFT plot appears normal, but performance is poor. **
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 ** The FFT window remains blank after the Run button is clicked ** ** The FFT window remains blank after the Run button is clicked **
-  * Make sure the evaluation board is securely connected to the hsc-adc-evale. +  * Make sure the evaluation board is securely connected to the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]]. 
-  * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the HSC-EVALE .  If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the  hsc-adc-evale setup process.+  * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]].  If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the  hsc-adc-evale setup process.
   * Make sure the correct FPGA //bin// file was used to program the FPGA.   * Make sure the correct FPGA //bin// file was used to program the FPGA.
   * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, and verify that the **Clock Frequency** is properly set.   * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, and verify that the **Clock Frequency** is properly set.
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 ** VisualAnalog displays a blank FFT when the RUN button is clicked ** ** VisualAnalog displays a blank FFT when the RUN button is clicked **
-  * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 24.{{ :eval:AD9684_clockdetect.png?600 |}}<WRAP centeralign>//Figure 24. Clock Detection Status Register//</WRAP>+  * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 28.{{ :eval:AD9684_clockdetect.png?600 |}}<WRAP centeralign>//Figure 28. Clock Detection Status Register//</WRAP>
  
resources/eval/ad9684-500ebz.1456515655.txt.gz · Last modified: 26 Feb 2016 20:40 by Jonathan Harris

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